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cml microcircuits communication semiconductor s cmx7131/CMX7141 digital pmr processor dpmr ? 2009 cml microsystems plc d/7131/41_fi-1.0/7 october 2009 datasheet advance information 7131/7141fi-1.x: dpmr baseband data processor with auxiliary system clocks, adcs and dacs features ? digital pmr ? dpmr (etsi ts 102 490) compliant ? air interface physical layer (layer 1) ? air interface data link layer (layer 2) ? 2 auxiliary adcs (4 multiplexed inputs) ? 4 auxiliary dacs ? 2 auxiliary system clock outputs ? tx outputs for two point or i/q modulation ? flexible powersave modes ? 4fsk modem ? 4.8 and 9.6 kbps data rates ? soft-decision data output option ? afsd (automated frame sync detection) ? raw data mode ? available in small lqfp or vqfn packages ? low-power (3.3v) operation ? c-bus serial interface to host controller ? vocoder connectivity ? vocoder management and control ? vocoder data transport ? two rf synthesisers (cmx7131 only) cmx7131/7141 digital pmr processor modulator rf discriminator host c system clock 1 system clock 2 cmx618 vocoder reference clock dac outputs adc inputs 3.0v to 3.6v built on firmasic ? technology gpio rxena txena rf synthesiser 1 rf synthesiser 2 cmx7131 only datasheet user manual this document contains:
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 2 d/7131/41_fi-1.0/7 1 brief description the 7131/7141fi-1.x function image? (fi) implements a half-duplex 4fsk modem and a large proportion of the dpmr air interface, data link and call control layers. in conjunction with a suitable host and a limiter/discriminator based rf transceiver, a compact, low cost, low power digital pmr radio conforming to etsi?s dpmr standard ts 102 490 c an be realised. dual mode, analogue/digital pmr operation can also be achieved with the cmx7131/CMX7141. both isf and csf configurations are supported, including built-in support for bcd addressing modes. the embedded functionality of the cmx7131/CMX7141, managing voice and data systems autonomously including cmx6x8 vocoder control (via the auxiliary spi/c-bus interface), minimises host microcontroller interactions enabling the lowest operating power and t herefore the longest battery life for a dpmr radio. the device utilises cml?s proprietary firmasic ? component technology. on-chip sub-systems are configured by a function image?: this is a data f ile that is uploaded during device initialisation and defines the device's function and feature set. the function image? can be loaded automatically from an external eeprom or host controller over the built-in c-bus serial interface. the device's functions and features may be enhanced by subsequent function image? releases, facilitating in-the-field upgrades. this document refers specific ally to the features provided by function image? 1.x. other features include two auxiliary adcs with four selectable inputs and four auxiliary dac interfaces (with an optional ramdac on the first dac output, to facilitate transmitter power ramping). additionally the cmx7131 features two on-chip rf synt hesisers, with easy rx/tx frequency changeover. the CMX7141 is identical in functionality to the cm x7131 with the exception t hat the two on-chip rf synthesisers have been deleted, which enables it to be supplied in a smaller package. this document refers to both parts, unless otherwise stated. the device has flexible powersaving modes and is available in both lqfp and vqfn packages. note that text shown in pale grey indicates features that will be supported in future versions of the function image?. this datasheet is the first part of a two-part document comprising datasheet and user manual: the user manual can be obtained by registering your interest in this product with your local cml representative.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 3 d/7131/41_fi-1.0/7 contents section page 1 brief descr iption.............................................................................................................. ....... 2 1.1 history........................................................................................................................ .. 5 2 block di agram .................................................................................................................. ...... 7 3 signal list.................................................................................................................... ............ 8 3.1 signal defi nitions....................................................................................................... 10 4 external co mponents .......................................................................................................... 11 4.1 recommended exter nal com ponents ...................................................................... 13 5 pcb layout guidelines and power supply decoupling................................................... 14 6 general d escripti on ............................................................................................................ . 16 6.1 7131/7141 fi-1.x features ........................................................................................ 16 6.2 system design .......................................................................................................... 17 6.3 introduc tion................................................................................................................ 18 6.3.1 modulat ion ........................................................................................................... 18 6.3.2 internal data processing ..................................................................................... 20 6.3.3 frame sync detecti on and demodul ation........................................................... 21 6.3.4 fec and c oding .................................................................................................. 24 6.3.5 voice c oding ....................................................................................................... 24 6.3.6 radio performanc e require ments ...................................................................... 24 7 detailed d escripti ons.......................................................................................................... . 25 7.1 xtal fr equency .......................................................................................................... 25 7.2 host inte rface ............................................................................................................ 25 7.2.1 c-bus oper ation................................................................................................. 25 7.3 function im age? loadi ng ........................................................................................ 27 7.3.1 fi loading from ho st cont roller .......................................................................... 27 7.3.2 fi loading from flash/ eeprom ......................................................................... 29 7.4 cmx618/cmx608 interface ...................................................................................... 30 7.5 device c ontrol ........................................................................................................... 30 7.5.1 general notes ..................................................................................................... 31 7.5.2 interrupt o peration .............................................................................................. 31 7.5.3 signal r outing ..................................................................................................... 31 7.5.4 modem c ontrol .................................................................................................... 32 7.5.5 tx mode (raw) .................................................................................................... 33 7.5.6 tx mode (prbs) ................................................................................................. 33 7.5.7 rx mode (raw).................................................................................................... 35 7.5.8 other modem modes........................................................................................... 36 7.5.9 data tr ansfer....................................................................................................... 36 7.5.10 cmx6x8 pass- through mode.............................................................................. 37 7.6 dpmr formatt ed operat ion ...................................................................................... 37 7.6.1 operating modes and addre ssing....................................................................... 37 7.6.2 isf addressing .................................................................................................... 38 7.6.3 csf addr essing .................................................................................................. 38 7.6.4 tx mode (dpmr formatted) ................................................................................. 38 7.6.5 rx mode (dpmr formatted)................................................................................. 40
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 4 d/7131/41_fi-1.0/7 7.6.6 slow data ............................................................................................................ 41 7.7 squelch o peratio n..................................................................................................... 41 7.8 gpio pin o peration................................................................................................... 42 7.9 auxiliary adc operation ........................................................................................... 42 7.10 auxiliary dac/ramd ac oper ation........................................................................... 43 7.11 rf synthesiser (cmx7131 only)............................................................................... 43 7.12 digital system cl ock gener ators .............................................................................. 47 7.12.1 main clock operation ......................................................................................... 47 7.12.2 system clock operation ..................................................................................... 48 7.13 signal level op timisation .......................................................................................... 48 7.13.1 transmit path levels .......................................................................................... 48 7.13.2 receive path levels ........................................................................................... 48 7.14 tx spectrum plots ..................................................................................................... 49 7.15 c-bus regist er su mmary ........................................................................................ 50 8 performance sp ecification .................................................................................................. 51 8.1 electrical pe rformance .............................................................................................. 51 8.1.1 absolute maxi mum ra tings................................................................................. 51 8.1.2 operating limits .................................................................................................. 52 8.1.3 operating char acteristics .................................................................................... 53 8.1.4 parametric pe rformance...................................................................................... 59 8.2 c-bus ti ming............................................................................................................ 60 8.3 packaging .................................................................................................................. 61 table page table 1 definition of powe r supply and refe rence vo ltages....................................................... 10 table 2 dpmr frame form at - call set- up, no ack .................................................................... 22 table 3 dpmr frame format - call set-up with ack................................................................... 22 table 4 xtal/clock frequency settings for progr am blo ck 3........................................................ 25 table 5 booten pin st ates ..................................................................................................... ... 27 table 6 modem mode sele ction .................................................................................................. . 32 table 7 modem c ontrol sele ction............................................................................................... .. 32 table 8 c-bus da ta registers .................................................................................................. ... 37 table 9 c-bu s regist ers....................................................................................................... ....... 50 figure page figure 1 bl ock di agram .................................................................................................................. 7 figure 2 CMX7141 recomm ended external component s .......................................................... 11 figure 3 cmx7131 recomm ended external component s .......................................................... 12 figure 4 CMX7141 power supply and de -couplin g ..................................................................... 14 figure 5 cmx7131 power supply and de -couplin g ..................................................................... 15 figure 6 digital voic e rx and tx blocks....................................................................................... 17 figure 7 4fsk prbs wave form - m odulation.............................................................................. 19 figure 8 4fsk prbs wa veform - spectrum................................................................................ 19 figure 9 dpmr modulat ion characte ristics .................................................................................. 20 figure 10 internal da ta processi ng blocks................................................................................... 21 figure 11 fs detection ........................................................................................................ ......... 23 figure 12 c-bu s transac tions .................................................................................................. ... 26 figure 13 fi loadi ng from host ................................................................................................ .... 28
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 5 d/7131/41_fi-1.0/7 figure 14 fi loadi ng from eeprom ............................................................................................ 29 figure 15 tx data fl ow (raw da ta mode) ................................................................................... 34 figure 16 rx data fl ow (raw da ta mode)................................................................................... 36 figure 17 auxadc irq oper ation................................................................................................ 43 figure 18 example rf synthesiser component s ........................................................................ 44 figure 19 single rf synt hesiser blo ck diagr am ......................................................................... 45 figure 20 digital clo ck generati on schem es............................................................................... 47 figure 21 tx modulat ion spectr a - 4800bps ................................................................................. 49 figure 22 tx modulat ion spectr a - 9600bps ................................................................................. 49 figure 23 c- bus ti ming........................................................................................................ ....... 60 figure 24 mechanical outli ne of 64-pin vqfn (q1)..................................................................... 61 figure 25 mechanical outli ne of 64-pin lqfp (l9) ...................................................................... 61 figure 26 mechanical outli ne of 48-pin lqfp (l4) ...................................................................... 62 figure 27 mechanical outli ne of 48-pin vqfn (q3)..................................................................... 62 information in this data sheet should not be relied upon for final product design. it is always recommended that you check for the latest product dat asheet version from the cml website: [ www.cmlmicro.com ]. 1.1 history version changes date 7 ? 3.1 added ? 6.2 (device control) revised ? 6.3 (dpmr description) revised ? 7.3 company standard text and diagrams used ? 7.4 6x8 supported modes clarified ? 7.5.6 prbs pattern conforms to en 300 113 ? 7.6.4 addition of ?silence? payload at vocoder start-up ? 7.11 references to rf ?channel? replaced by rf ?synthesiser? 06.10.09 6 ? cmx7131 features added ? modulation diagram updated to latest (fig 9) ? note added that 9600bps mode does not support automated cmx6x8 operation (6.3) ? c-bus timing diagram updated to latest (fig 23) ? ramdac timing updated to latest ? gpio1&2 defined as rx and tx enable ? c-bus signal names standardised ? contact details updated ? document style normalised 21.4.09 8.5.09 29.6.09 5 ? slow data support for type 1 and type 2 data modes ? bcd wildcard reporting added ? additional binary group call id?s added ? fs detect flow chart and text added (normal and late entry calls) ? internal processing block diagram added ? slow data irq added ? parametric specifications clarified 10.11.08 4 ? slow data in voice mode added ? corrected auxadc conversion time ? extended xtal f low to 3mhz ? fine input attenuation removed 22.07.08
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 6 d/7131/41_fi-1.0/7 3 ? removal of c11 to ensure dc coupling of disc input for 4-level fsk (4fsk) modulation ? updated function image? software release list 25.06.08 2 ? first released document, prepared for first beta release of software 19.11.07 1 ? original document, prepared for internal use mid 2007 this is advance information; changes and additions may be made to this specification. parameters marked tbd or left blank will be included in later iss ues. items that are highlighted or greyed out should be ignored. these will be clarified in later issues of this document. information in this datasheet should not be relied upon for final product design.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 7 d/7131/41_fi-1.0/7 2 block diagram alt txena rxena gpioa gpiob mod2 adc1 adc2 adc3 adc4 epsclk booten1 booten2 epcsn sysclk1 sysclk2 avdd vbias avss xtal/clk xtaln epso epsi multiplexed adcs dacs system clocks system control internal signal mux function image? configured io mux adc 1 thresholds averaging thresholds averaging system clock 1 system clock 2 c-bus interface irqn rdata sclk power control registers spi eeprom interface bias dvdd vdec dvss bias crystal oscillator boot control main pll auxiliary functions adc 2 filtering 4fsk modem demodulator cdata csn tx mode select gpio rx data buffer v bias v bias mic rx signal routing mod1 tx modulator v bias disc ssout filtering tx data buffer audio mux core operations tx and rx interfacing audio o/p afsd soft-decision decoding payload decoding 4fsk modem modulator payload coding rx functions tx functions external vocoder control external vocoder control dac1 dac2 dac3 dac4 dac 1 dac 2 dac 3 dac 4 ramp profile ram rf synthesiser 1 rf synthesiser 2 rf1n cp1out iset1 rf2n cp2out iset2 rfvdd cpvdd rfvss rfclk rf synthesisers (cmx7131 only) rf1p rf2p figure 1 block diagram
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 8 d/7131/41_fi-1.0/7 3 signal list cmx7131 64-pin q1/l9 CMX7141 48-pin q3/l4 signal name type description 1 8 irqn op c-bus: a 'wire-orable' output for connection to the interrupt request input of the host. pulled down to dv ss when active and is high impedance when inactive. an external pull-up resistor (r1) is required. 2 - rf1n ip rf synthesiser #1 negative input 3 - rf1p ip rf synthesiser #1 positive input 4 - rfvss pwr rfv ss : the negative supply rail (ground) for the 1st rf synthesiser 5 - cp1out op 1st charge pump output 6 - iset1 ip 1st charge pump current set input 7 - rfvdd pwr rfv dd : the 2.5v positive supply ra il for the rf synthesisers. this should be decoupled to rfv ss by a capacitor mounted close to the device pins. 8 - rf2n ip rf synthesiser #2 negative input 9 - rf2p ip rf synthesiser #2 positive input 10 - rfvss pwr rfv ss : the negative supply rail (ground) for the 2nd rf synthesiser. 11 - cp2out op 2nd charge pump output 12 - iset2 ip 2nd charge pump current set input 13 - cpvdd pwr the 3.3v positive supply rail fo r the rf charge pumps. this should be decoupled to rfv ss by a capacitor mounted close to the device pins. 14 - rfclk ip rf clock input (common to both synthesisers) 1 15 - gpioa op general purpose i/o pin (7131 only) 16 - gpiob op general purpose i/o pin (7131 only) 17 - - nc reserved? do not connect this pin 18 9 vdec pwr internally generated 2.5v digi tal supply voltage. must be decoupled to dv ss by capacitors mounted close to the device pins. no other connections a llowed, except for optional connection to rfv dd . 19 10 rxena op rx enable ? active lo w when in rx mode ($c1:b0 = 1) - 11 gpioa op general purpose i/o pin (7141 only) - 12 gpiob op general purpose i/o pin (7141 only) 20 13 sysclk1 op synthesised digital system clock output 1 21 14 dvss pwr dv ss digital ground 22 - - nc reserved ? do not connect this pin 23 15 txena op tx enable ? active low when in tx mode ($c1:b1 = 1) 1 to minimise crosstalk, this signal should be connected to the same clock source as xtal / clock input.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 9 d/7131/41_fi-1.0/7 cmx7131 64-pin q1/l9 CMX7141 48-pin q3/l4 signal name type description 24 16 disc ip channel 1 inverting input 25 17 discfb op channel 1 input amplifier feedback 26 18 alt ip channel 2 inverting input 27 19 altfb op channel 2 input amplifier feedback 28 20 micfb op channel 3 input amplifier feedback 29 21 mic ip channel 3 inverting input 30 22 avss pwr av ss analogue ground 31 23 mod1 op modulator 1 output 32 24 mod2 op modulator 2 output 33 25 vbias op internally generated bias voltage of about av dd /2, except when the device is in ?powersave? mode when v bias will discharge to av ss . must be decoupled to av ss by a capacitor mounted close to the device pi ns. no other connections allowed. 34 26 audio op reserved for future use 2 35 27 adc1 ip auxiliary adc input 1 36 28 adc2 ip auxiliary adc input 2 37 29 adc3 ip auxiliary adc input 3 38 30 adc4 ip auxiliary adc input 4 each of the two adc blocks can select its input signal from any one of these input pins, or from the mic, alt or disc input pins. see section 10.1.3 for details. 39 31 avdd pwr av dd : analogue +3.3v supply rail. levels and thresholds within the device are proportional to this voltage. this pin should be decoupled to av ss by capacitors mounted close to the device pins. 40 32 dac1 op auxiliary dac output 1/ramdac 41 33 dac2 op auxiliary dac output 2 42 34 avss pwr av ss : analogue ground 43 35 dac3 op auxiliary dac output 3 44 36 dac4 op auxiliary dac output 4 - 37 dvss pwr dv ss : digital ground 45 38 vdec pwr v dec : internally generated 2.5v supply voltage. must be decoupled to dv ss by capacitors mounted close to the device pins. no other connections allo wed, except for the optional connection to rfv dd . 46 39 xtal/clk ip input from the ex ternal clock source or xtal 47 40 xtaln op the output of the on-chip xt al oscillator inverter. nc if external clock used. 48 41 dvdd pwr dv dd : digital +3.3v supply rail. this pin should be decoupled to dv ss by capacitors mounted cl ose to the device pins. 2 the audio out pin is not currently used in this fi, however it has been included here for compatibility with future products.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 10 d/7131/41_fi-1.0/7 cmx7131 64-pin q1/l9 CMX7141 48-pin q3/l4 signal name type description 49 42 cdata ip c-bus command data: serial data input from the c 50 43 rdata ts op c-bus reply data: a 3-state c-bus serial data output to the c. this output is high im pedance when not sending data to the c. 51 44 ssout op spi bus chip select/frame sync (used for cmx6x8) 52 45 dvss pwr dv ss :digital ground 53 - - nc reserved ? do not connect this pin 54 46 sclk ip c-bus serial clock: the c-bus serial clock input from the c. 55 47 sysclk2 op synthesised digital system clock output 2 56 48 csn ip c-bus chip select: the c-bus ch ip select input from the c - there is no internal pullup on this input 57 - - nc reserved ? do not connect this pin 58 1 epsi op eeprom serial interface: spi bus output 59 2 epsclk op eeprom serial interface: spi bus clock 60 3 epso ip+pd eeprom serial interface: spi bus input 61 4 epscsn op eeprom serial inte rface: spi bus chipselect 62 5 booten1 ip+pd used in conjunction with booten2 to determine the operation of the bootstrap program. 63 6 booten2 ip+pd used in conjunction with booten1 to determine the operation of the bootstrap program. 64 7 dvss pwr dv ss :digital ground e xposed m etal p ad e xposed m etal p ad substrate ~ on this device, the central metal pad (which is exposed on q1 and q3 packages only) may be electrically unconnected or, alternatively, may be connected to analogue ground (avss). no other electrical connection is permitted. notes: ip = input (+ pu/pd = internal pullup / pulldown resistor) op = output bi = bidirectional ts op = 3-state output pwr = power connection nc = no connection - should not be connected to any signal. 3.1 signal definitions table 1 definition of power supply and reference voltages signal name pins usage av dd avdd power supply for analogue circuits dv dd dvdd power supply for digital circuits v dec vdec power supply for core logic, derived from dv dd by on-chip regulator v bias vbias internal analogue reference level, derived from av dd av ss avss ground for all analogue circuits dv ss dvss ground for all digital circuits
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 11 d/7131/41_fi-1.0/7 4 external components figure 2 CMX7141 recommended external components
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 12 d/7131/41_fi-1.0/7 figure 3 cmx7131 recommended external components
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 13 d/7131/41_fi-1.0/7 4.1 recommended external components r1 100k c1 18pf c11 not used c21 10nf r2 100k c2 18pf c12 100pf c22 10nf r3 100k c3 10nf c13 see note 5 c23 10nf r4 100k c4 not used c14 100pf c24 10f r5 see note 2 c5 1nf c15 see note 5 r6 100k c6 100pf c16 200pf r7 see note 3 c7 100nf c17 10f r8 100k c8 100pf c18 10nf x1 6.144mhz r9 see note 4 c9 100pf c19 10nf see note 1 r10 100k c10 not used c20 10f resistors 5%, capacitors and inductors 20% unless otherwise stated. notes: 1. x1 can be a crystal or an external clock gener ator; this will depend on the application. the tracks between the crystal and the device pins should be as short as possible to achieve maximum stability and best start up performance. by default, a 19.2mhz oscillator is assumed (in which case c1 and c2 are not required), other values could be used if the various internal clock dividers are set to appropriate values. 2. r5 should be selected to provide the desired dc gain of the discriminator input, as follows: ? gain disc ? = 100k / r5 the gain should be such that the resultant output at the discfb pin is within the disc input signal range specified in 7.13.2. for 4fsk modulation, this signal should be dc coupled from the limiter/ discriminator output. 3. r7 should be selected to provide the desired dc gai n (assuming c13 is not present) of the alternative input as follows: ? gain alt ? = 100k / r7 the gain should be such that the re sultant output at the altfb pin is within the alternative input signal range specified in 7.13. 4. r9 should be selected to provide the desired dc gain (assuming c15 is not present) of the microphone input as follows: ? gain mic ? = 100k / r9 the gain should be such that the resultant output at the micfb pi n is within the microphone input signal range specified in 7.13.1. for optimum performance with low signal microphones, an additional external gain stage may be required. 5. c13 and c15 should be selected to maintain the lower frequency roll-off of the mic and alt inputs as follows: c13 1.0f ? gain alt ? c15 30nf ? gain mic ? 6. alt and altfb connections allow the user to have a second discriminator or microphone input. component connections and values are as for the respec tive disc and mic networks. if this input is not required, the alt pin should be connected to av ss . 7. c5 (audio) should be increased to 1.0f if frequencies below 300hz need to be used on this pin. 8. a single 10f electrolytic capacitor (c24, fi tted as shown) may be used for smoothing the power supply to both vdec pins, providing they are connected together on the pcb with an adequate width power supply trace. alternativ ely, separate smoothing capacit ors should be connected to each vdec pin. high frequency decoupling capacitors (c3 and c23) must always be fitted as close as possible to both vdec pins.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 14 d/7131/41_fi-1.0/7 5 pcb layout guidelines and power supply decoupling figure 4 CMX7141 power supply and de-coupling component values as per figure 2
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 15 d/7131/41_fi-1.0/7 figure 5 cmx7131 power supply and de-coupling component values as per figure 3 notes: it is important to protect the analogue pins from extraneous inband noise and to minimise the impedance between the cmx7131/CMX7141 and the supply and bias de- coupling capacitors. the de-coupling capacitors c3, c7, c18, c19, c21, c22 and c24 should be as close as possible to the cmx7131/CMX7141. it is therefore re commended that the printed circuit board is laid out with separate ground planes for the av ss and dv ss supplies in the area of the cmx7131/CMX7141, with provision to make links between them, close to the cmx7131/CMX7141. use of a multi- layer printed circuit board will facilitate the provision of gr ound planes on separate layers. v bias is used as an internal reference for detecti ng and generating the various analogue signals. it must be carefully decoupled, to ensure its integrity, so apart from the decoupling capacitor shown, no other loads should be connected. if v bias needs to be used to set the discriminator mid-point reference, it should be buffered with a high input impedance buffer. the single ended microphone input and audio output must be ac coupled (as shown), so that their return paths can be connected to av ss without introducing dc offsets. fu rther buffering of the audio output is advised. the crystal, x1, may be replaced with an external clock source.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 16 d/7131/41_fi-1.0/7 6 general description 6.1 7131/7141 fi-1.x features the 7131/7141 fi-1.x function image? is intended for use in half duplex digital pmr equipment using 4fsk modulation at 4800 or 9600 bps suitable for 6.25khz and 12.5khz channel systems. much of the dpmr etsi ts 102 490 standard air in terface protocol is embedded in the 7131/7141fi-1.x function image? operation namely: air interface physical layer 1 ? 4fsk modulation and demodulation ? bit and symbol definition ? frequency and symbol synchronisation ? transmission burst building and splitting air interface data link layer 2 ? channel coding (fec, crc) ? interleaving, de-interleaving and bit ordering ? frame and superframe building and synchronising ? burst and parameter definition ? link addressing (source and destination) ? interfacing of voice applications (voi ce data) with the physical layer ? data bearer services ? exchanging signalling and/or user data with the call control layer ? automatic own-id and group-id detection a flexible power control facility allows the device to be placed in its optimum powersave mode when not actively processing signals. the device includes a crystal clock generator, with bu ffered output, to provide a common system clock if required. a block diagram of the device is shown in figure 1. the signal processing blocks can be routed from any of the three disc/alt/mic input pins. other functions include: ? automatic tx sequencer simplifies host control ? ramdac operation ? txena and rxena hardware signals ? two-point or i/q modulation outputs ? hard or soft data output options analogue pmr functionality: ? complete audio processing ? ctcss/dcs signalling auxiliary functions: ? two programmable system clock outputs ? two auxiliary adcs with four se lectable external input paths
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 17 d/7131/41_fi-1.0/7 ? four auxiliary dacs, one with built-in programmable ramdac ? two rf plls (cmx7131 only) interface: ? optimised c-bus (4 wire high speed synchronous serial command/data bus) interface to host for control and data transfer ? open drain irq to host ? auxiliary spi/c-bus interface to cmx 618/cmx608 with pass-through mode from host ? two gpio pins ? eeprom boot mode ? c-bus (host) boot mode 6.2 system design figure 6 shows one possible implementation of the CMX7141 combined with a cmx618, a host controller and suitable rf sections to provide a digita l pmr radio. the bold lines show the active signal paths in rx and tx respectively. figure 6 digital voice rx and tx blocks cmx618 cmx618 host host CMX7141 CMX7141 rf section vocoder disc txmod1 txmod2 paramp spi port c-bus clk c-bus datain c-bus csn0 c-bus dataout mic spkr modem de- coding rf section vocoder disc txmod1 txmod2 paramp spi port c-bus clk c-bus datain c-bus csn0 c-bus dataout mic spkr modem coding audio codec audio codec squelch rx_ena tx_ena squelch rx_ena tx_ena protocol protocol
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 18 d/7131/41_fi-1.0/7 the paralleling of the microphone and speaker connections between the cmx618 and the cmx7131/CMX7141 is only required if the cmx7131/CMX7141 is also to provide analogue pmr functionality (implemented using 7031/7041 fi1.x) . otherwise, the microphone and speaker should be connected to the cmx618 only. t he cmx618 ralcwi vocoder provides an on-chip audio and voice codec, but alternatively a cmx608 device could be used along with an external audio codec. voice payload data is transferred directly from and to the cmx618 by the cmx7131/CMX7141, but if a third- party vocoder is used, all data will need to be tr ansferred over the main c-bus through the host. the auxadc provided by the cmx7131/CMX7141 can be used to detect t he squelch or rssi signal from the rf section while the device is in rx or idle modes. this allows a significant degree of powersaving within the cmx7131/CMX7141 and avoids the need to wake the host up unnecessarily. the host programmable auxadc thresholds allow for user selection of squelch threshold settings. when transmitting, an initial block of payload or c ontrol channel data will need to be loaded from the host into the c-bus txdata registers. the cmx7131/CMX7141 can then format and transmit that data while at the same time loading in the following data blocks from the host or cmx618. when receiving, the host needs to understand that when a signal is received over the air there will be a processing delay while the cmx7131/CMX7141 filters, demodulates and decodes the output data before presenting it to the host or cmx618. for best performance voice payload data can be output in soft- decision (4-bit log-likelihood ratio) format compat ible with the cmx618/cmx608 and other third-party vocoders, although this mode increases the data trans fer rate over c-bus by a factor of four. 6.3 introduction this modem can run at either 4800bps or 9600bps, o ccupying a 6.25khz or a 12.5khz bandwidth rf channel respectively. it has been designed such that, w hen combined with suitable rf, host controller, cmx618/cmx608 vocoder and appropriate control softwar e, it meets the requi rements of the en 301 166 or en 300 113 standards as appropriate. see www.etsi.org for details of these standards. ts 102 490 is available on the etsi web site ( www.etsi.org ) which describes a 6.25khz channel spacing fdma dpmr system. this standard uses a 4fsk modul ation scheme with an over-air bit rate of 4800bps (ie. 2400 symbols per second). with respect to dp mr formatted modes of operation, this document should be read in conjunction with the etsi standard. the dpmr standard does not specify a voice codi ng algorithm, but the cmx618 or cmx608 (also available from cml) are both suitable devices for this purpose. in the rest of this document these two devices are referred to generically as the cmx6x8, as the only significant difference between them is the inclusion of an on-chip audio codec in the cmx618 wh ile the cmx608 requires an external audio codec. note that the ts 102 490 (dpmr) standard is not compatible with the ts 102 362 (dmr) 12.5khz/9600baud tdma system. the 9600bps option is made available for customer-s pecific applications only ? this mode does not support automated control of the cmx6x8 ? in wh ich case all data should be routed via the host. 6.3.1 modulation the dpmr 4fsk modulation scheme operates in a 6. 25khz channel bandwidth with a deviation index of 0.29 and has an over-air bit rate of 4800bps (2400 sy mbols per second). rrc filters are implemented in both tx and rx with a filter ?alpha? of 0.2. the maximum frequency error is +/-625hz and the cmx7131/CMX7141 can adapt to the maximum time-base clock drift of 2ppm over the duration of a 180- second burst. figure 9 shows the basic parameters of the 4fsk modulation, symbol mapping and filtering requirements. the 9600bps mode provided by the cmx7131/CMX7141 is essentially the same as the 4800bps mode, but with all timings modified by a factor of two. figure 7 and figure 8 show a transmitted prbs waveform, as recorded on a spectrum analyser in 36k span and zero-span mode, having been 2-point m odulated using a suitable rf transmitter.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 19 d/7131/41_fi-1.0/7 r e f l v l 3 0 d b m 3 0 d b m r e f l v l 3 0 d b m 3 0 d b m 3 0 d b o f f s e t a s t a r t 0 s s t o p 3 5 m s c f 4 4 6 . 1 m h z d e m o d b w : 1 0 0 k h z r e a l t i m e o f f a f - s i g n a l f m [ h z ] 5 0 0 1 v i e w - 2 k - 1 . 5 k - 1 k - 5 0 0 0 5 0 0 1 k 1 . 5 k 2 k - 2 . 5 k 2 . 5 k 1 m a r k e r 1 [ t 1 ] 3 1 . 3 9 9 1 8 m s f m 6 6 1 . 9 8 7 h z 1 [ t 1 ] 3 1 . 3 9 9 1 8 m s f m 6 6 1 . 9 8 7 h z d 1 1 . 0 5 k h z d 2 - 1 . 0 5 k h z d a t e : figure 7 4fsk prbs waveform - modulation a r b w 1 0 0 h z v b w 1 k h z s w t 1 8 s u n i t d b m 1 r m 3 0 . 8 d b o f f s e t r e f l v l 3 0 d b m r e f l v l 3 0 d b m r f a t t 2 0 d b 3 . 6 k h z / c e n t e r 4 4 6 . 1 m h z s p a n 3 6 k h z - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 1 0 2 0 - 7 0 3 0 1 m a r k e r 1 [ t 1 ] 1 6 . 4 8 d b m 4 4 6 . 1 0 0 1 0 8 2 2 m h z 1 [ t 1 ] 1 6 . 4 8 d b m 4 4 6 . 1 0 0 1 0 8 2 2 m h z c h p w r 2 7 . 5 3 d b m a c p u p - 6 6 . 5 5 d b a c p l o w - 6 7 . 1 4 d b a l t 1 u p - 7 9 . 4 5 d b a l t 1 l o w - 8 0 . 2 1 d b c u 2 c u 2 c u 1 c u 1 c l 1 c l 1 c l 2 c l 2 c 0 c 0 d a t e : figure 8 4fsk prbs waveform - spectrum
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 20 d/7131/41_fi-1.0/7 0 = | f | < ( 1 - ) / 2t | h ( f ) | = cos[ ( t/4 )( 2 | f | - ( 1 - ) / t] ( 1 + ) / = | f | ( 1 - ) / = | f | < ( 1 + ) / 2t , , , 1 0 = 0.2 t = 1/2400 tx baseband filter 4 fsk deviation di-bit symbol deviation 01 2 +3 +1 050hz +350hz -350hz -1050hz +1 -1 -3 00 2 10 2 11 2 rx baseband filter frequency demod fm if signal h( f ) filter d( f ) filter information bits output 0 = | f | < ( 1 - ) / 2t | h ( f ) | = cos[ ( t/4 )( 2 | f | - ( 1 - ) / t] ( 1 + ) / = | f | ( 1 - ) / = | f | < ( 1 + ) / 2t , , , 1 0 | d ( f ) | = sin ( f t ) f t = 0.2 t = 1/2400 frequency modulator 4fsk output information bits input h( f ) filter d( f ) filter | d ( f ) | = sin ( f t ) f t figure 9 dpmr modulation characteristics 6.3.2 internal data processing the cmx7131/CMX7141 operates as a half-dupl ex device, either receiving si gnals from the rf circuits in rx mode, or sourcing signals to the rf circuits in tx mode. it also has a low power idle mode to support battery saving protocols. the internal data proce ssing blocks for tx and rx modes are illustrated in figure 10.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 21 d/7131/41_fi-1.0/7 c-bus port data buffer frame type detect fec interleave scramble packet formatter data router spi-port (from 6x8) 4-fsk modulator filter i/q look-up mux filter afsd 4-fsk demod frame type detect de-interleave de-scramble de-fec data router spi-port (to 6x8) data buffer address matcher c-bus port packet de- formatter disc input mod1 output mod2 output raw data raw data control info control info voice data voice data figure 10 internal data processing blocks 6.3.3 frame sync detection and demodulation the analogue signal from the limiter/discriminator of the external rf section should be applied to one of the cmx7131/CMX7141 inputs (normally the disc input) where it can be adjusted to the correct level either by selection of the feedback resistor or using the cmx7131/CMX7141 input gain settings. the signal is filtered using a root-raised cosine filter and in verse rx sinc filter matching the filters applied in the transmitter, then passed to the afsd (automated fr ame sync detector) block which extracts symbol and frame synchronisation. during this process t he 4fsk demodulator and the following data-processing sections are dormant to minimise power consum ption. when frame synchronisation has been achieved the afsd section is powered down, and timing and sy mbol-level information is passed to the 4fsk demodulator which starts decoding the subsequent data bits. in raw mode the demodulator will continue operating until the host switches it o ff, but in dpmr formatted mode the cmx7131/CMX7141 can detect the end of a call by scanning the received control channel fields and will automatically disable the demodulator and restart frame sync search when required without host intervention. a dpmr call begins with a 72-bit or longer pr eamble sequence followed by an 80ms header frame, which contains a 48-bit frame sync (fs1 or fs4) . subsequent payload frames contain either a 24-bit frame sync (fs2) or a 24-bit colour code. the cmx7131/CMX7141 can scan for all dpmr frame syncs concurrently. it uses fs1 to detect the start of a transmission, and this is reported to the host by setting the fs1 detect bit in the irq status register. it can also optionally use fs2 to perform ?late entry? into an existing call, reported by setting the fs2 detect bi t. the short length of fs2 gives a high probability of false detections, so by default the cmx7131/CMX7141 will only generate an fs 2 detect if two successive fs2 frame syncs are detected at the corre ct frame spacing in the received signal. in raw mode operation, 24-bit frame sync detecti on is disabled but both the preamble and the 48-bit frame sync sequences are user-progr ammable (see user manual sections 10.2.1). in dpmr formatted mode, the frame syncs and preamble defined in ts 102 490 are always used regardless of the programmed raw mode frame syncs. in both case s, when frame synchronisation has been achieved and the 4fsk demodulator is enabled, frame sync detecti on is switched off and any subsequent frame sync sequences embedded in the received data are not reported to the host.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 22 d/7131/41_fi-1.0/7 table 2 dpmr frame format - call set-up, no ack bit no. 24 48 72 96 120 144 168 192 216 240 264 288 312 336 360 384 press ptt header tx cc frame 1 tx fs2 cch payload payload payload payload frame 2 tx cc cch payload payload payload payload frame 3 tx fs2 cch payload payload payload payload frame 4 tx cc cch payload payload payload payload frame 1 tx fs2 cch payload payload payload payload frame 2 tx cc cch payload payload payload payload frame 3 tx fs2 cch payload payload payload payload frame 4 tx cc cch payload payload payload payload tx repeat frames 1 to 4 until ptt released?. end tx fs3 header info 1 header info 0 end flag preamble fs1 table 3 dpmr frame format - call set-up with ack bit no. 24 48 72 96 120 144 168 192 216 240 264 288 312 336 360 384 press ptt header tx cc end tx fs3 ack rx cc header tx cc frame 1 tx fs2 cch payload payload payload payload frame 2 tx cc cch payload payload payload payload frame 3 tx fs2 cch payload payload payload payload frame 4 tx cc cch payload payload payload payload frame 1 tx fs2 cch payload payload payload payload frame 2 tx cc cch payload payload payload payload frame 3 tx fs2 cch payload payload payload payload frame 4 tx cc cch payload payload payload payload tx repeat frames 1 to 4 until ptt released?. end tx fs3 preamble fs1 header info 0 header info 1 header info 1 header info 0 end flag preamble fs1 header info 0 preamble fs1 header info 1 end flag
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 23 d/7131/41_fi-1.0/7 rx enabled afsd active 4fsk dormant fs1 detected? afsd off 4fsk active irq fs1 fs2 detected? afsd off 4fsk active irq fs2 demodulate demodulate irq fs2 cc detected? fs2 detected? id & cc matched? irq called irq datardy (hdr + le) enable 6x8 transfer data to 6x8 end detected? irq datardy (end) no no no no no no id & cc matched? no process data afsd process analyse cch data decode, de-interleave analyse hdr data decode, de-interleave irq called irq datardy (hdr) disable 6x8 figure 11 fs detection
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 24 d/7131/41_fi-1.0/7 6.3.4 fec and coding in raw mode the cmx7131/CMX7141 does not implem ent any fec processing. in dpmr formatted mode the cmx7131/CMX7141 implements all crcs , hamming codes, interleaving and scrambling required by the dpmr standard. crc failures in control channel fields and coded data blocks are indicated to the host by issuing an ?ev ent? irq with a corresponding error code in the modem status register, $c9. this relieves the host of a substantial processing load and has the added advantage of reducing the complexity and timing constraints of interfacing between the host, vocoder and cmx7131/CMX7141. the dpmr header frame format contains duplicate copi es of all control channel fields (in the hi0 and hi1 header information blocks) but only one decoded copy of each field will be presented back to the host. on receiving a header frame the cmx7131/CMX7141 decodes both hi blocks, checks crcs and can accept the call if either block is va lid (the other hi block is discarded). 6.3.5 voice coding a cml cmx618 or cmx608 ralcwi vocoder can be used under the control of the cmx7131/CMX7141. the cmx7131/CMX7141 provides an auxiliary spi/c-bus port (shared with the boot eeprom) which is used to issue control commands and transfer voice payload data directly to the cmx6x8 vocoder, minimising the loading on the host controller during voice calls. alternatively, the cmx7131/CMX7141 can support any third-party vocoder by routing voice payload data over the main c-bus interface and through the host. in this mode, all vocoder control and data transfers must be managed by the host. voice data transferred to the cmx6x8 in rx mode alwa ys uses soft decision (4-bit log-likelihood ratio) format. this option is also available for voice pay load data routed to the host, although it increases the required data transfer rate over c-bus by a factor of four. 6.3.6 radio performance requirements the cmx7131/CMX7141 demodulator is designed to process a 4fsk signal from a limiter / discriminator source. for optimum performance the signal should not be significantly degraded by filters that are excessively narrow and / or cause significant group delay distortion. care should be taken in interfacing the device to the radio circuits to maintain t he frequency and phase response (both low and high end), in order to achieve optimum performance. test modes ar e provided to assist in both the initial design and production set-up procedures. further information and application notes can be found at http://www.cmlmicro.com .
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 25 d/7131/41_fi-1.0/7 7 detailed descriptions 7.1 xtal frequency the cmx7131/CMX7141 is designed to work with an exter nal frequency source of 19.2mhz. if this default configuration is not used, then progr am register block 3 must be loaded with the correct values to ensure that the device will work to specif ication with the user selected clo ck frequency. a table of common values can be found in table 4. note the maximum xtal frequenc y is 12.288mhz, although an external clock source of up to 24mhz can be used. the register values in table 1 are shown in hex, the default settings are shown in bold, and the settings which do not give an exact setting (but are within accept able limits) are in italics. the new p3.2-3 settings take effect following the write to p3.3 (the settings in p3.4-7 are implemented on a change to rx or tx mode). table 4 xtal/clock frequency settings for program block 3 program register external frequency source (mhz) 3.579 6.144 9.216 12. 0 12.8 16.368 16.8 19.2 p3.2 gp timer $017 $018 $018 $019 $019 $018 $019 $018 p3.3 idle vco output and aux clk divide $085 $088 $08c $10f $110 $095 $115 $099 p3.4 ref clk divide $043 $040 $060 $07d $0c8 $155 $15e $0c8 p3.5 pll clk divide $398 $200 $200 $200 $300 $400 $400 $200 p3.6 vco output and aux clk divide $140 $140 $140 $140 $140 $140 $140 $140 p3.7 rx or tx internal adc/dac clk divide $008 $008 $008 $008 $008 $008 $008 $008 7.2 host interface a serial data interface (c-bus) is used for command, status and data transfers between the cmx7131/CMX7141 and the host c; this interface is compatible with microwire and spi. interrupt signals notify the host c when a change in status has occurred and the c should read the status register across the c-bus and respond accordingly. in terrupts only occur if the appropriate mask bit has been set. see section 7.5.2. the cmx7131/CMX7141 will monitor the stat e of the c-bus registers that the host has written-to every 250s (the c-bus latency period) hence it is not advisabl e for the host to make successive writes to the same c-bus register within this period. 7.2.1 c-bus operation this block provides for the transfer of data and control or status information between the cmx7131/CMX7141?s internal registers and the host c over the c-bus serial interface. each transaction consists of a single address byte sent from the c which may be followed by one or more data byte(s) sent from the c to be written into one of the cmx7131/CMX7141?s write only registers, or one or more data byte(s) read out from one of the cmx7131/CMX7141?s read only registers, as shown in figure 12. data sent from the c on the cdata (c ommand data) line is clocked into the cmx7131/CMX7141 on the rising edge of the sclk (serial clock) input. rdata (reply data) sent from the cmx7131/CMX7141 to the c is valid when the sclk is high. the csn line must be held low during a data transfer and kept high between transfers. the c-bus interface is compat ible with most common c serial interfaces and may also be easily implemented with general purpose c i/o pins controlled by a simple software routine.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 26 d/7131/41_fi-1.0/7 the number of data bytes following an address byte is dependent on the value of the address byte. the most significant bit of the address or data is sent first. for detailed timings see section 8.2. note that, due to internal timing constraints, there may be a del ay of up to 250s between the end of a c-bus write operation and the device reading the dat a from its internal register. c-bus write: see note 1 see note 2 csn sclk cdata 7 6 5 4 3 2 1 0 7 6 ? 0 7 ? 0 msb lsb msb lsb msb lsb address/command byte upper 8 bits lower 8 bits rdata high z state c-bus read: see note 2 csn sclk cdata 7 6 5 4 3 2 1 0 msb lsb address byte upper 8 bits lower 8 bits rdata 7 6 ? 0 7 ? 0 high z state msb lsb msb lsb data value unimportant repeated cycles either logic level valid (and may change) either logic level valid (but must not change from low to high) figure 12 c-bus transactions notes: 1. for command byte transfers only the fi rst 8 bits are transferred ($01 = reset). 2. for single byte data transfers only the first 8 bits of the data are transferred. 3. the cdata and rdata lines are never active at the same time. the address byte determines the data direction for each c-bus transfer. 4. the sclk input can be high or low at the start and end of each c-bus transaction. 5. the gaps shown between each byte on the cda ta and rdata lines in the above diagram are optional, the host may insert gaps or concatenate the data as required.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 27 d/7131/41_fi-1.0/7 7.3 function image? loading the function image? (fi), which defines the operati onal capabilities of the device, may be obtained from the cml technical portal, following registration. this is in the form of a 'c' header file which can be included into the host controller software or programm ed into an external eeprom or flash memory. the maximum possible size of function image tm is 46 kbytes, although a typical fi will be less than this. note that the booten pins are only read at power-on or following a c-bus general reset and must remain stable throughout the fi loading process. once the fi load has completed, the booten pins are ignored by the cmx7131/CMX7141 until the next power-up or c-bus general reset. the booten pins are both fitted with internal low current pull-down devices. for c-bus load operation, both pins shoul d be pulled high by connecting them to dv dd either directly or via a 47k resistor (see figure 13). for flash/eeprom load, only booten1 needs to be pull ed high in a similar manner, however, if it is required to program the eeprom or flash memory in-situ from the host, either a jumper to dv dd or a link to a host i/o pin should be provided to pull booten2 high when required (see figure 14). once the fi has been loaded, the cmx7131/CMX7141 performs these actions:- (1) the product identification code ($7141 or $7131) is reported in c-bus register $c5 (2) the fi version code is r eported in c-bus register $c9 (3) the two 32-bit fi checksums are reported in c-bus register pairs $a9, $aa and $b8, $b9 (4) the device waits for the host to load the 32-bi t device activation code to c-bus register $c8 (5) once activated, the device initialises fu lly, enters idle mode and becomes ready for use. the checksums can be verified against the published val ues to ensure that the fi has loaded correctly. once the fi has been activated, the checksum, pr oduct identification and version code registers are cleared and these values are no longer available. if an invalid activation code is loaded, the device will report the value $dead in register $a9 and must be power cycled before an attempt is made to re-load the fi and re-activate. both the device activation code and the checksum values are available from the cml technical portal. table 5 booten pin states booten2 booten1 c-bus host load 1 1 reserved 1 0 flash/eeprom load 0 1 no fi load 0 0 note: in the rare event that a g eneral reset needs to be issued without the requirement to re-load the fi, the booten pins must both be cleared to '0' before t he command is issued. the checksum values will be reported and the device activation code will need to be sent in a similar manner as that shown in figure 14. there will not be any fi loading delay. this a ssumes that a valid fi has been previously loaded and that v dd has been maintained throughout the reset to preserve the data. 7.3.1 fi loading from host controller the fi can be included into the host controller software build and downloaded into the cmx7131/CMX7141 at power-up over t he c-bus interface. the booten pins must be set to the c-bus load configuration, the cmx7131/CMX7141 powered up and placed in to program mode, the data can then be sent directly over the c-bus to the cmx7131/CMX7141. if the host detects a brownout, the booten state shoul d be set to re-load the fi. a general reset should then be issued and the appropriate fi load procedure followed. each time the programming register, $c8, is written, it is necessary to wait for the prg flag (irq status register ($c6) b0) to go high before another write to $c8. the prg flag going high confirms the write to
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 28 d/7131/41_fi-1.0/7 the programming register has been accepted. the pr g flag state can be determined by polling the irq status register or by unmasking the inte rrupt (interrupt mask register, $ce, b0). the download time is limited by the clock frequency of t he c-bus, with a 5mhz sclk, it should take less than 500ms to complete. booten 2 = 1 booten 1 = 1 power-up or write general reset to device poll $c6 until b0 = 1 (programming mode entered) configure prg flag interrupt if required write $0001 to $c8 write start block 1 address (db1_ptr) to $b6 write block 1 length (db1_len) to $b7 wait for prg flag to go high or interrupt write next data word to $c8 wait for prg flag to go high or interrupt write start block 2 address (db2_ptr) to $b6 write block 2 length (db2_len) to $b7 write $0001 to $c8 wait for prg flag to go high or interrupt wait for prg flag to go high or interrupt write next data word to $c8 write start block 3 address (activate_ptr) to $b6 write block 3 length (activate_len) to $b7 write $0001 to $c8 wait for prg flag to go high or interrupt send activation code hi to $c8 read and verify checksum values in register pair : $a9 and $aa, $b8 and $b9 send activation code lo to $c8 wait for prg flag to go high or interrupt wait for prg flag to go high or interrupt booten1 and booten2 may be changed from this point on, if required device is now ready for use booten1 booten2 vdd figure 13 fi loading from host
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 29 d/7131/41_fi-1.0/7 7.3.2 fi loading from flash/eeprom the fi must be converted into a format for t he flash/eeprom programmer (normally intel hex) and loaded into the eeprom or flash memory either by the host or an external programmer. the cmx7131/CMX7141 needs to have the b ooten pins set to flash/eeprom load, and then on power-on, or following a c-bus general reset, the cmx7131/CMX7141 will automatica lly load the data from the eeprom or flash memory without inte rvention from the host controller. booten 2 = 0 booten 1 = 1 power-up or write general reset to device poll $c6 until b0 = 1 (fi loaded) configure prg flag interrupt if required send activation code hi to $c8 read and verify checksum values in register pair : $a9 and $aa, $b8 and $b9 send activation code lo to $c8 wait for prg flag to go high or interrupt wait for prg flag to go lo or interrupt booten1 and booten2 may be changed from this point on, if required device is now ready for use booten1 booten2 vdd jumper for programming eeprom (if required) figure 14 fi loading from eeprom the cmx7131/CMX7141 has been designed to function wi th atmel at25hp512 serial eeprom and the at25f512 flash eeprom devices 3 , however other manufacturers parts may also be suitable. the time taken to load the fi is dependant on the xtal frequency, with a 19.2mhz xtal, it should load in less than 1 second. 3 note that these two devices have slightly different addressing schemes. cmx7131/CMX7141 is compatible with both schemes, whereas previous fi ?s were only compatible with the at25hp512 addressing scheme.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 30 d/7131/41_fi-1.0/7 7.4 cmx618/cmx608 interface an auxiliary spi/c-bus interface is provided which allows the cmx6x8 to be directly controlled by the cmx7131/CMX7141 without the need for the host to in tervene. this is accomplished by re-using the eeprom spi interface with an additional chip select pin (ssout). the eeprom data out pin must not drive the signal line when the chip is not enabled, otherwise the cmx6x8 will not be able to return its data to the cmx7131/CMX7141. the cmx7131/CMX7141 spi serial bus should be connected to the c- bus interface on the cmx6x8 using the ssout pin as the csn signal for the cmx6x8. the initialisation and operational settings of the cm x6x8 should be programmed by the host into the cmx7131/CMX7141 program block 1 on power-up. these values will be written to the defined registers in the cmx6x8 at: o initialisation o idle mode o rx mode o tx mode mic gain and speaker gain commands may be sent to the cmx6x8 whenever the cmx7131/CMX7141 is in rx or tx mode. the dtx and vad modes of the cmx6x8 are not s upported in fi-1. dtmf mode 1 (transparent) is supported. the default settings for the cmx6x8 are: o 4 frame packet (80ms) with fec no std, no dtmf o 2400bps with fec o internal sync o throttle = 1 o internal codec o irq disabled o soft coded data bits 7.5 device control the cmx7131/CMX7141 can be set into the relevant m ode to suit its environment. these modes are described in the following sections and are programmed over the c-bus: either directly to operational registers or, for parameters that are not likely to change during operation, via the programming register ($c8). for basic operation: (1) enable the relevant hardware sections via the power down control register (2) set the appropriate mode registers to the desired state (3) select the required signal routing and gain (4) use the mode control register to place the device into rx or tx mode to conserve power when the device is not actively processing a signal, place the device into idle mode. this will also command the cmx6x8 to enter power saving mode as well. additional powersaving can be achieved by disabling any unused hardware blocks, how ever, care must be taken not to disturb any sections that are automatically c ontrolled. note that the bias block must be enabled to allow any of the input or output blocks to function. see: o power down control - $c0 write o modem control - $c1 write o modem configuration - $c7 write
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 31 d/7131/41_fi-1.0/7 7.5.1 general notes in normal operation, the most significant registers, in addition to the txdata and rxdata blocks, are: o modem control - $c1 write o irq status - $c6 read o analogue output gain - $b0 write o input gain and signal routing - $b1 write o auxdata write - $c2 write o cmx6x8 analogue gain- $c3 write setting the mode register to either rx or tx will aut omatically increase the internal clock speed to its operational speed and bring the cmx6x8 out of its pow ersave mode, whilst setting the mode register to idle will automatically return the internal clock to a lower (powersaving) speed. to access the program blocks (through the programming register, $c8) the device must be in idle mode. under normal circumstances the cmx7131/CMX7141 manages the main clock control automatically, using the default values loaded in program block 3. 7.5.2 interrupt operation the cmx7131/CMX7141 will issue an interrupt on the irqn line when the irq bit (bit 15) of the irq status register and the irq mask bit (bit 15) are both set to 1. the irq bit is set when the state of the interrupt flag bits in the irq status register change from a 0 to 1 and the corresponding mask bit(s) in the interrupt mask register is(are) set. enabling an interrupt by setting a mask bit (0 1) after the corresponding irq status register bit has already been set to 1 will also cause the irq bit to be set. all interrupt flag bits in the irq status register, except the programming flag (bit 0), are cleared and the interrupt request is cleared following the command/addr ess phase of a c-bus read of the irq status register. the programming flag bit is set to 1 only when it is permissible to write a new word to the programming register. see: o irq status - $c6 read o interrupt mask - $ce write 7.5.3 signal routing the cmx7131/CMX7141 offers a flexible routing architectu re, with three signal inputs, a choice of two modulator configurations (to suit 2-point m odulation or i/q schemes) and a single audio output. see: o input gain and signal routing - $b1 write o modem control - $c1 write o modem configuration - $c7 write the analogue gain/attenuation of each input and output can be set individually, with additional fine attenuation control available via the programming registers in the cmx7131/CMX7141. the mic. and speaker gains are set by the cmx6x8, which is controlled through the cmx6x8 analogue gain- $c3 write of the cmx7131/CMX7141. see: o analogue output gain - $b0 write (tx mod1 and 2) o input gain and signal routing - $b1 write (rx disc input, tx mod1 and 2) o cmx6x8 analogue gain- $c3 write (cmx6x8 mic. and speaker) in common with other fis developed for the cmx7131/CMX7141, this device is equipped with two signal processing paths. however, in this implementation of the fi, input 2 is not currently used and so should not be enabled. input 1 should be routed to either of the three input sources (alt, disc or mic) which should be connected to the radio?s discriminator outpu t. the internal signals output 1 and output 2 are
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 32 d/7131/41_fi-1.0/7 used to provide either 2-point or i/q signals and should be routed to the mod1 and mod2 pins as required. in dpmr formatted modes the microphone and speaker pat hs are automatically re-routed to the cmx6x8 vocoder when appropriate. this routing is controlled by the data field in the header block which indicates whether the payload data is voice or data and the enable bit in the modem control register, $c1. 7.5.4 modem control the cmx7131/CMX7141 operates in one of these operational modes: o idle o rx o tx o cmx6x8 pass-through at power-on or following a reset, the device will autom atically enter idle mode, which allows maximum powersaving whilst still retaining the capability of monitoring the auxadc inputs (if enabled). it is only possible to write to the programming register whilst in idle mode. see: o modem control - $c1 write gpio1 and gpio2 pins (rxena and txena) reflect bi ts 0 and 1 of the modem control register, as shown in table 6. these can be used to drive external hardware without the host having to intervene. there are also two additional gpio pins t hat are programmable under host control. table 6 modem mode selection modem control ($c1) b0-3 modem mode gpio2 - txena gpio1 - rxena 0000 idle ? low power mode 1 1 0001 rx 1 0 0010 tx 0 1 0011 reserved x x 0100 cmx6x8 pass-through 1 1 0101 reserved x x 0110 reserved x x 0111 reserved x x 1xxx reserved x x the cmx6x8 pass-through mode is used to control and monitor the cmx6x8 directly. this cannot be accessed if the cmx7131/CMX7141 is in rx or tx modes. this mode will transfer data to/from the txdata0/rxdata0 register to the cmx6x8 c-bus register address spec ified in the programming register ($c8). see section 7.5.10. the modem control bits are ignored in this mode. table 7 modem control selection 4fsk modem control ($c1) b7-4 rx tx 0000 rx idle tx idle 0001 rx 4fsk formatted tx 4fsk formatted 0010 rx 4fsk raw tx 4fsk raw 0011 rx 4fsk eye tx 4fsk prbs 0100 reserved tx 4fsk preamble 0101 reserved tx 4fsk mod set-up 0110 sync test 0111 reset/abort reset/abort 1xxx reserved reserved the modem mode bits and the modem control bits s hould be set together in the same c-bus write.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 33 d/7131/41_fi-1.0/7 in tx mode, the cmx7131/CMX7141 can operate as a raw m ode data pump or in dpmr formatted mode. in both cases the first block of control c hannel or payload data should be loaded into the c-bus txdata registers before exec uting the mode change. a ?datar eady? irq will be issued when the registers have been read by the cmx7131/CMX7141 and the host can t hen supply further blocks of payload data. when all payload has been transmitted the cmx7131/CMX7141 will issue a ?txdone? irq and the host can then reset the mode bits to either rx or idle as required. in rx mode the received signal should be routed through input1 (disc). in raw and dpmr formatted modes the cmx7131/CMX7141 will first search for fram e synchronisation, and when this has been achieved the following data is demodulated and supplied to the host through the rxdata registers. a ?dataready? irq indicates when each new blo ck becomes available. in raw mode the cmx7131/CMX7141 will continue demodulati ng the input signal until the host resets the mode bits to tx or idle, but in dpmr formatted mode the modem can detect the end of a call and restart frame sync search automatically. 7.5.5 tx mode (raw) in raw mode tx operation ($c1, modem control = $0022), the preamble and frame sync are transmitted automatically (default values for raw mode may be changed by use of the program registers) and data from the txdata block is then transmitted directly until the mode is changed to rx, pass-through or idle. the first block of data should be loaded into the tx data registers before ex ecuting the modem mode change to tx. data is transmitted msb (most significant bit) first. the host should write the initial data to the c-bu s txdata registers and then set the modem mode to txraw and the mode bits to tx. as soon as the data block has been read from the c-bus txdata registers, the datardy irq will be assert ed and the next block of data may be loaded. when the host stops loading data into the device a data underflow condition will eventually occur. after the last data bit has left the modulator a ?txdone? irq w ill be issued. at this point it is now safe for the host to change the modem control and modem mode to idle ($c1, modem control = $0000) and turn the rf transmitter off. 7.5.6 tx mode (prbs) in prbs mode tx operation ($c1, modem control = $0023) the preamble and frame sync are transmitted automatically followed by a prbs pattern conforming to itu-t o.153 (para 2.1) giving a 511-bit repeating sequence.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 34 d/7131/41_fi-1.0/7 load data to c-bus txdatablock transaction count =0, byte count =9 set modem control to: txraw, mode = tx irq = datardy? no gpio2 and gpio1 will change to 01 and the modem will transmit the preamble, frame sync and data the host should ensure that any external hardware is also set into tx mode (if not automatically controlled by the gpio pins). note: yes more data to send? load data to c-bus txdatablock transaction count ++, byte count =9 yes no see rx_process flow diagram note: set modem control to idle: mode = idle gpio2 and gpio1 will change to 11 and the modem will drop into idle mode. the host should ensure that any external hardware is also set into idle mode (if not automatically controlled by the gpio pins). note: goto rx_process goto idle mode ramdac has been enabled data is in 9 byte blocks note: tx_process irq = txdone? no yes irq=error, modem status = underflow may occur at this point, if enabled. note: due to internal processing delays in the filters etc, the host should wait for irq=txdone or implement its own delay to ensure all data has been transmitted. note: execute ramdac down execute ramdac up ensure that ramdac speed is fast enough to allow for hardware and internal processing delays note: figure 15 tx data flow (raw data mode)
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 35 d/7131/41_fi-1.0/7 7.5.7 rx mode (raw) in rx raw mode operation ($c1, modem control = $0021), the cmx7131/CMX7141 automat ically starts searching for frame synchronisation. when a valid fr ame sync sequence is detected, an ?fs1 detect? or ?fs2 detect? irq is asserted and the data demodulat or is enabled. all following payload data is loaded directly into the c-bus rxdata registers with a ?dataready? irq to indicate when each new block is available. this continues until the mode is changed to idle or tx, even if the call has ended and there is no longer a valid signal at the input. the host must respond to each ?dataready? irq before the rxdata registers are overwritten by subsequent payload data blocks. if ?soft? data mode has been selected, the payload data is encoded in 4-bit log-likelihood-ratio format. in this mode the host must be able to service the ?datar eady? irqs and rxdata regist ers at four times the normal rate to avoid overflow. note that raw mode operation always requires the in coming data to be preceded with a valid frame sync sequence in order to derive timing information for the demodulator.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 36 d/7131/41_fi-1.0/7 rx_process set modem control to: rxraw, mode = rx irq = datardy? no gpio2 and gpio1 will change to 10, the modem will start to look for frame sync. the host should ensure that any external hardware is also set into rx mode (if not automatically controlled by the gpio pins). note: yes more data to receive? load data from c-bus rxdatablock check transaction count and byte count yes no see tx_process flow diagram note: set modem control to: rxidle, mode = idle gpio2 and gpio1 will change to 11, and the modem will drop into idle mode. the host should ensure that any external hardware is also set into idle mode (if not automatically controlled by the gpio pins). note: goto tx_process goto idle_process ramdac has been enabled data is in 9 byte blocks note: if enabled , irq=framesync will occur before irq=datardy note: an irq=datardy may still be pending at this point note: figure 16 rx data flow (raw data mode) 7.5.8 other modem modes in rx 4fsk eye mode the filtered received signal is output at the mod1 pin as an ?eye? diagram for test and alignment purposes. a trigger pulse is output at the mod2 pin to allow viewing on a suitable oscilloscope. the trigger pulse is generated directly fr om the receiver xtal source, not from the input signal. in tx mode a number of test and set-up modes are provided to facilitate test and alignment. o prbs (preamble and synchronisation word are automatically transmitted first) o continuous preamble: a repeating sequenc e of [+3 +3 -3 -3] symbols o modulation set-up: in 2-point mode, a repeating sequence of eight +3 symbols followed by eight - 3 symbols, and in i/q mode a cont inuous sequence of +3 symbols. 7.5.9 data transfer payload data is transferred from/to the host using blocks of five rx and five tx 16-bit c-bus registers, allowing up to 72 bits (9 bytes) of data to be transfe rred in sequence. the lowest 8 bits of the register block are reserved for a byte counter, block id and a transaction counter. the byte count indicates how
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 37 d/7131/41_fi-1.0/7 many bytes in the data block are va lid and avoids the need to perform a full five word c-bus read/write if only a smaller block of data need to be transferred. table 8 c-bus data registers c-bus address function c-bus address function $b5 tx data 0-7 & info $b8 rx data 0-7 & info $b6 tx data 8-23 $b9 rx data 8-23 $b7 tx data 24-39 $ba rx data 24-39 $ca tx data 40-55 $bb rx data 40-55 $cb tx data 56-71 $c5 rx data 56-71 the block id is ignored in raw mode, but should be set to 01 (payload) for consistency with dpmr formatted mode (see user manual section 10.1.17 ). bits 7 and 6 hold the transaction counter, which is provided to allow detection of missed transfers and underflow/overflow. during a call, in rx mode the cmx7131/CMX7141 increments the counter (modulo 4) on each transfer via the rxdata block, and in tx mode the host must increment the counter on every write to the txdata block. in tx mode the cmx7131/CMX7141 detects that new dat a from the host is available by the change in the value of the transaction counter, so it is vital that the txdata0 register, which contains the counter, is the last txdata regist er to be written to in each transaction. if the cmx7131/CMX7141 identifies that a bl ock has been written out of sequenc e, an event irq will be issued. 7.5.10 cmx6x8 pass-through mode to allow the host to communicate directly with t he cmx6x8 for test and configuration purposes, a pass- through mode is available which allows any cmx6 x8 c-bus register to be read or written (as appropriate). this mode uses the txdata0, rx data0 and programming registers on the CMX7141. to write to the cmx6x8: o set the cmx7131/CMX7141 to cmx6x8 pass-through mode ($c1=$0004) o wait for the program flag to be set ($c6 b0) o write the cmx6x8 data value to the txdata0 register ($b5) o write the cmx6x8 c-bus address to the programming register ($c8) with b15=0 o wait for the program flag to be set ($c6 b0) to read from the cmx6x8: o set the cmx7131/CMX7141 to cmx6x8 pass-through mode ($c1=$0004) o wait for the program flag to be set ($c6 b0) o write the cmx6x8 c-bus address to the programming register ($c8) with b15=1 o wait for the program flag to be set ($c6 b0) o read the cmx6x8 data value from the rxdata0 register ($b8) cmx6x8 c-bus addresses are all 8 bits long and s hould be written to bits 0-7 of the programming register. bit 15 is the read/write flag (0 = read, 1 = write) and bit 14 is the register-size flag (0 = 16-bit, 1 = 8-bit). unused bits should be cleared to zero. w hen an 8-bit register is read or written, the data occupies the lower 8 bits of the appropria te data register (txdata0 or rxdata0). 7.6 dpmr formatted operation in dpmr formatted mode the cmx7131/CMX7141 performs all frame building/splitting and fec coding/decoding, which relieves the host controller of a significant processing load. during voice calls the cmx7131/CMX7141 can automatically enable and control the cmx6x8, and transfer voice payload data from/to it without host intervention. in rx mode the cmx7131/CMX7141 monitors address fields in incoming transmissions and only accepts calls if t he programmed address requirements are satisfied. this allows the host to remain in a power-down or ?s leep? state until it is rea lly necessary to wake up, extending the battery life of the final product design. 7.6.1 operating modes and addressing ts 102 490 describes two operating modes for a dpmr radio:
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 38 d/7131/41_fi-1.0/7 o isf ? initial services and fac ilities ? ?out of the box? mode o csf ? configured services and facilities ? ?managed? mode the cmx7131/CMX7141 can support either of these modes, as selected by b9 of the modem configuration register, $c7 (see user manual section 10.1.27). the standard also defines two addressing schemes: 24-bi t binary or 7-digit bcd (binary-coded-decimal). radios operating in isf mode are required to use bi nary addressing, but in csf mode either binary or bcd addressing can be used. both addressing schemes are supported by the cmx7131/CMX7141, selected by b11 in the modem configurati on register, $c7 (see user manual section 10.1.27). the host can load two own ids (binary or bcd) into program block 1 for use in both tx and rx modes. in tx mode the host can select which of these to send in the ?caller id? field of the outgoing call. in rx mode the cmx7131/CMX7141 compares the ?called id? field from incoming calls against each of its own ids, and will accept the call if a valid id match is found. address matching can be disabled using b12 of the modem configuration regist er, $c7 in which case the cmx7131/CMX7141 will accept all incoming calls. the cmx7131/CMX7141 implements bcd address translation in both tx and rx, to relieve the host of the processing required to map bcd digits to over-a ir binary values. bcd addresses can include wildcard digits in any of the lower four digits, and there are ten bcd ?all-call? addresses with wildcards in all six lower digits. the cmx7131/CMX7141 handles wildcard digits appropriately during address matching in rx . binary addresses do not support group calling with wildcards, but the cmx7131/CMX7141 provides six binary-only group call ids in addition to the two own ids. these can be programmed by the host to be used for address matching in rx only. ts 102 490 also specifies a system-wide all call fac ility using the ?communication format? field in the header frame (ts 102 490 section 5.8). the normal setting for this field is ?peer-to-peer?, but when set to ?call all? the cmx7131/CMX7141 will always accept the call regardless of isf/csf mode and all other address settings. the host should take care not to transmit in all call mode unless actually intended. 7.6.2 isf addressing the services available in isf mode are described in ts 102 490 section 8.1. radios using isf mode provide a style of operation broadly similar to analogue pmr446. isf mode requires 24-bit binary addressing to be used, wi th only the top 8 bits (the common id field) in active use for addressing isf mode devices. the remain ing 16 bits must be set to all 1s. this is the default mode of the cmx7131/CMX7141 and the default common ids are: o id1: $01 o id2: $02 the isf common all-call id is $ff. when in isf mode the cmx7131/CMX7141 will always accept calls to this address regardless of other address settings. 7.6.3 csf addressing the services available in csf mode are de scribed in ts 102 490 section 8.2 and annex a. csf mode does not mandate bcd addre ssing unless the host implements the standard user interface, but the advantages of bcd addressing are direct mapping of user keypad entries to destination addresses and the option of wildcard digits to implement group calls. the host can select the addressing mode using b11 of the modem configuration register, $c7. 7.6.4 tx mode (dpmr formatted) device operation in tx dpmr formatted mode ($c1 , modem control = $0012) is similar to raw mode operation but the cmx7131/CMX7141 builds header, control channel and end information blocks, performs all fec coding, interleaving and scrambling functions and inserts frame sync and colour code sequences to generate the required frame format s for transmission. during voice calls the cmx7131/CMX7141 can automatically enable and control the cmx6x8, and transfer voice payload data from/to it without host intervention.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 39 d/7131/41_fi-1.0/7 the txdata registers are used to transfer header and end information fields in addition to payload data. the block id field in the txdata0 register informs the cmx7131/CMX7141 how to process each transfer. b5-4 block id 00 hdr - header data 01 pld - payload data 10 pls - payload data with slow data 11 end - end data the host should preload the txdata registers with header data before placing the device in tx dpmr formatted mode. the cmx7131/CMX7141 reads the ?header type? field to determine the burst type and then sends the preamble and header frame. if the ?c all information? field indicates that repeated ?extended wake-up? headers are to be sent, the cmx7131/CMX7141 will do so automatically. the header fields are saved for re-use when building the control channel information blocks in following payload frames: the host does not need to re-load them. header data: txdata rxdat a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 reserved own id header type counter 0 0 1 0 0 1 1 le 0 call information comms mode 2 comms format 0 0 0 0 0 0 colour code 0 0 0 0 binary mode: called address lower 12 bits 3 bcd mode: called address lower 4 digits k4, k5, k6, k7 0 0 0 0 binary mode: called address upper 12 bits 4 0 0 0 0 bcd mode: called address upper 3 digits k1, k2, k3 header type: see ts 102 490 section 5. 11 (communication start, ack, etc.) own id: 00 = reserved 01 = send own id 1 (from program block 1) 10 = send own id 2 (from program block 1) 11 = reserved reserved : see ts 102 490 section 5.4 (00) comms mode: see ts 102 490 section 5.7 (s ets data type and source, host or vocoder) le: late-entry (rx only) ? some data fi elds may be missing due to late entry into the call call information: see ts 102 490 section 5.10 (i ncludes extended headers, dat a frame size etc.) comms format: see ts 102 490 section 5.8 (all-call or peer-to-peer) colour code: 6-bit index into the colour code table as shown in ts 102 490 section 6.1.5 payload data: see table 8 and user manual section 10.1.14 payload data with slow data: see table 8 and user manual section 10.1.14 end data: txdata rxdat a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 tx wait ack req end type counter 1 1 0 0 1 1 1 0 0 0 0 0 0 reserved 0 status message 2 not used 3 not used 4 not used
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 40 d/7131/41_fi-1.0/7 end type: see ts 102 490 section 5.12 ack request: see ts 102 490 section 5.13 tx wait: see ts 102 490 section 5.14 status msg: see ts 102 490 section 5.15 reserved : 0000 depending on the burst type, the cmx7131/CMX7141 will expect the host to load a series of payload data blocks and/or an end data block (except for ack bursts which consist of a bare header frame). disconnect bursts contain a repeated header/end frame pair but the host should only load single blocks of header and end data fields, as the cmx7131/CMX7141 will send the duplic ate frames automatically. if the cmx6x8 vocoder is enabled and the ?communication mode? field in the header frame indicates a voice call, the cmx7131/CMX7141 will automatically enable the cmx6x8 microphone input and route payload data from the cmx6x8 for transmission. note t hat the cmx6x8 takes a finite time to encode the incoming voice data, during which the cmx7131/CMX7141 will automatically in sert ?silence? data into the payload frames. the host can load an end frame at any poi nt during the call. to terminate the voice call, the host should place the cmx7131/CMX7141 modem into tx idle mode ($c1, modem control = $0002). the cmx7131/CMX7141 will disable the cmx6x8 and send the end frame that was loaded previously. at the end of all dpmr transmissions the cmx7131/CMX7141 will issue a txdone irq when it is safe for the host to place the device back into idle mode ($c1, modem control = $0000). 7.6.5 rx mode (dpmr formatted) device operation in rx dpmr formatted mode ($c1 , modem control = $0011) is similar to raw mode operation but the cmx7131/CMX7141 automatically splits incoming calls to extract header information, control channel information and end information bl ocks and performs all the necessary de-scrambling, de-interleaving and fec decoding functions. in speech calls the cmx7131/CMX7141 can automatically enable the cmx6x8 vocoder when required and transfer received speech data without host intervention. the rxdata registers are used to transfer header and end data fields in addition to payload data. the block id field in the rxdata0 register informs the host what type of data block each transfer contains. the field layout in the rxdata register s for the different transfer types is the same as for tx dpmr formatted mode (section 7.6.4). when placed in rx dpmr formatted mode the cmx7131/CMX7141 automatically starts searching for the dpmr frame sync sequences. in addition to detecting the 48-bit fs1 frame sync at the start of a transmission, the cmx7131/CMX7141 can also perform ?late entry? into a call by detecting two successive copies of the 24-bit fs2 sequence at the co rrect two-frame spacing. when a valid frame sync sequence has been detected, an ?fs1 detect? or ?fs2 detect? irq is issued and the data demodulator is enabled. the cmx7131/CMX7141 then decodes the contents of the header frame (a fter an fs1 detect) or the following four control channel information blocks (after an fs2 detect). the header information or control channel information crcs are checked and proce ssing continues only if a full set of valid fields has been received. header frames contain tw o duplicate header information blocks: the cmx7131/CMX7141 checks both block crcs, uses t he first valid block and discards the other. when repeated ?extended wake-up? header frames ar e received (see ts 102 490 section 11.1) the cmx7131/CMX7141 will decode the first valid header but delay address checking until all following repeat headers have been received. this maximises the time the host can be kept in powersave. address checking now takes place depending on isf/ csf mode and the addressing mode selected. the ?communications format? field is checked first: if this is set to ?call all? the call is accepted. if not, the ?called station id? is checked against the device?s ow n ids (programmed by the host into program block 1) and if a match is found the call is accepted. in isf mode the common all-call id $ff is also always accepted. in any of these cases a ?called? irq is issued to the host, otherwise the call is dropped with no further host notification and the cmx7131/CMX7141 returns to frame sy nc search. address matching can be disabled by setting b12 of the modem conf iguration register, in which case the cmx7131/CMX7141 will accept all incoming calls. the header fields are presented to the host in the rx data block. late entry is indicated by bit 15 of rxdata1: in this case the ?header type? and ?call inform ation? fields in the header data block returned to
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 41 d/7131/41_fi-1.0/7 the host will not contain valid data, as these fields are only sent in header frames and are not re-sent in the control channel information blocks during a call. depending on the burst type the cmx7131/CMX7141 will decode the following payload and/or end frames and present their contents to the host or vocoder. if the cmx6x8 vocoder is enabled and the ?communication mode? field in the header frame indicates a voice call, the cmx7131/CMX7141 will automatically enable the cmx6x8 speaker output and r oute payload data to the cmx6x8 for decoding. in this mode, the data is transferred in 4-bit log- likelihood-ratio format. otherwise payload data is presented to the host in the rxdata registers in soft or hard format as specified. when an end frame is received the cmx7131/CMX7141 will report its contents to t he host, disable the vocoder (if necessary) and return to frame sync search. all frame sync sequences, colour codes and crcs contained in payload superframes are checked and an ?event? irq is issued when any are received incorrectly. if all the frame sync sequences, colour codes and crcs in a superframe are received incorre ctly, the superframe is considered corrupt. the host can set a threshold for consecutive corrrupt s uperframes (in program block 0) after which the cmx7131/CMX7141 will issue an ?event? irq, drop the call and return to frame sync search. see: o rxdata 0 - $b8 read o auxdata read - $cc read 7.6.6 slow data slow data may be transferred in voice calls alongsi de voice payload data, by setting the block id to ?payload with slow data? and using the auxdata r egisters. if the cmx6x8 is enabled, there will be no voice payload transfers and so dummy payload transfers are used with the byte counter field cleared to zero. in type1 and type 2 data calls the slow data field is used to control the data flow over-air and so is generated or decoded by the cmx7131/CMX7141 itself and the only data fiel d that is visible to the host is the ?format? field as defined in ts 102 490 section 5. 9.2. which is made avail able, or supplied by the host, in the lowest 4 bits of the auxdata register. in tx mode: o load auxdata register with two bytes of slow data: auxdata write - $c2 write o set communications mode to ?voice with slow data? o set blockid to ?payload with slow data?: txdata 0 - $b5 write o set byte counter field (to zero if cmx6x8 is in use): txdata 0 - $b5 write the cmx7131/CMX7141 has an internal 64-byte buffer for sl ow data. while the host keeps this internal data buffer ?topped-up? the cmx7131/CMX7141 will continue to transmit slow data and add the ?continuation bits? to the over-air data. note that only two bytes of slow data are sent over-air for every 36 bytes of voice payload, so the buffer may overflow if a large quantity of slow data is loaded continuously. an irq bit will be raised when there ar e only two bytes left in the fifo. when the host allows the internal buffer to empty, the cmx7131/CMX7141 will terminate the transmission of slow data in the current burst. it is not possibl e to re-s tart slow data transmission within a burst. in rx mode: o blockid will report ?payload with slow data?: rxdata 0 - $b8 read o communications mode will report ?voice with slow data? o if payload is being sent to the cmx6x8, then t he byte counter field will be cleared to zero o slow data is available in the auxdata register: auxdata read - $cc read when the slow data transfer has completed, the cmx7131/CMX7141 will stop pr esenting data to the host. 7.7 squelch operation many limiter/discriminator chips provide a noise-quieting squelch circuit around an op-amp configured as a filter. this signal is conventionally passed to a com parator to provide a digital squelch signal, which can be routed directly to one of the cmx7131/CMX7141?s gpio pins or to the host. however with the
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 42 d/7131/41_fi-1.0/7 cmx7131/CMX7141, the comparator and threshold operations can be replaced by one of the auxadcs with programmable thresholds and hysteresis functions. see: o irq status - $c6 read o modem configuration - $c7 write 7.8 gpio pin operation the cmx7131/CMX7141 provides 4 pins. rxena (gpio1) and txena (gpio2) are configured to reflect the tx/rx state of the mode regist er (txena and rxena, active low). see: o modem configuration - $c7 write note that rxena and txena will not change state until the relevant mode change has been executed by the cmx7131/CMX7141. this is to allow the host sufficient time to load the relevant data buffers and the cmx7131/CMX7141 time to encode the data required prior to its transmission. there is thus a fixed time delay between the gpio pins changing state and t he data signal appearing at the mod output pins. during the power-on sequence (until the fi has comp leted its load sequence) these pins have only a weak pull-up applied to them, so care should be tak en to ensure that any loading during this period does not adversely affect the operation of the unit. gpio a and b are host programmable for input or output using the auxadc confi guration register, $a7. the default state is output, high level. when set for input, the values can be read back using the modem status register, $c9. 7.9 auxiliary adc operation the inputs to the two auxiliary adcs can be independently routed from any of the signal input pins under control of the auxadc configuration register, $a7. conversions will be performed as long as a valid input source is selected. to stop the adcs, the input source should be set to ?off?. register $c0, b6, bias, must be enabled for auxiliary adc operation. averaging can be applied to the adc readings by selecti ng the relevant bits in the auxadc configuration register, $a7, the length of the averaging is determined by the value in the programming register (p3.0 and p3.1), and defaults to a value of 0. this is a rolling average system such that a proportion of the current data will be added to the last average value. the proportion is determined by the value of the average counter in p3.0 and p3.1. for an average value of: 0 = 50% of the current value will be added to 50% of the last average value, 1 = 25% of the current value will be added to 75% of the last average value, 2 = 12.5% etc. the maximum useful value of this field is 9. high and low thresholds may be independently applied to both adc channels (the comparison is applied after averaging, if this is enabled) and an irq gener ated when a rising edge passes the high threshold or a falling edge passes the low threshold, see figure 17. the thresholds are programmed via the auxadc threshold register, $cd. see figure 17.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 43 d/7131/41_fi-1.0/7 signal ir q ir q ir q ir q high threshold low threshold figure 17 auxadc irq operation auxiliary adc data is read back in the auxadc data registers ($a9 and $aa) and includes the threshold status as well as the actual conversi on data (subject to averaging, if enabled). see: o auxadc configuration - $a7 write o auxadc1 data and status - $a9 read o auxadc2 data and status - $aa read o auxadc threshold data - $cd write 7.10 auxiliary dac/ramdac operation the four auxiliary dac channels are programmed via t he auxdac data/control r egister, $a8. auxdac channel 1 may also be programmed to operate as a ramdac which will automatically output a pre- programmed profile at a programmed rate. the auxdac data/control register, $a8, with b12 set, controls this mode of operation. the default profile is a raised cosine (see table 13), but this may be over-written with a user-defined profile by writing to progra mming register p3.11. the ramdac operation is only available in tx mode and, to avoid glitches in the ramp profile, it is important not to change to idle or rx mode whilst the ramdac is still ramping. the auxd ac outputs hold the user-programmed level during a powersave operation if left enabled, otherwise they will return to zero. note that access to all four auxdacs is controlled by the auxdac data/control register, $a8, and therefore to update all auxdacs requires four writes to this r egister. it is not possible to simultaneously update all four auxdacs. see: o auxdac data/control - $a8 write 7.11 rf synthesiser (cmx7131 only) the cmx7131 includes two integer-n rf synthesisers, each comprising a divider, phase comparator and charge pump. the divider has two sets of n and r registers: one set can be used for transmit and the other for receive. the division ratios can be set up in advance by means of c-bus registers. a single c- bus command will change over from the transmit to the receive division ratios, or vice versa, enabling a fast turnaround. see: o rf synthesiser data - $b2 write o rf synthesiser control - $b3 write o rf synthesiser status - $b4 8-bit read
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 44 d/7131/41_fi-1.0/7 external rf components are needed to complete the synthesiser circuit. a typical schematic for a 446mhz synthesiser (3.125khz co mparison frequency) is shown in figure 18. cmx7131 + - rf output rfnp rfnn rfv ss rfv dd cpv dd charge pump dividers and phase detector rfv ss r31 rfv ss vco c35 c34 r33 c33 c32 r32 c31 cpnout isetn reference frequency note: n = 1 or 2 for synthesiser 1 or 2 r34 figure 18 example rf synthesiser components r31 0 c31 22nf r32 5.6k c32 470nf r33 10k c33 10nf r34 100 c34 1nf c35 1nf resistors 5%, capacitors and inductors 20% unless otherwise stated. note: r31 is chosen within the range 0 to 30k and selects the nominal charge pump current. it is recommended that c34 and c35 are kept clos e to the vco and that the stub from the vco to the cmx7131 is kept as short as possible. the loop filter components should be placed close to the vco.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 45 d/7131/41_fi-1.0/7 figure 19 single rf synthesiser block diagram the two rf synthesisers are programmable to any frequency in the range 100mhz to 600mhz. figure 19 is a block diagram of one synthesiser channel. the rf synthesiser clock is selectable between the xtal or the clock supplied to the rfclk input pin. the rf synthesiser clock is co mmon to both synthesisers. the charge pump supply (cp supply, cpvdd) is al so common to both synthesisers. the rfnp and rfnn input pins, cpnout, isetn and rfvss pins ar e channel specific and designated as either rf1p, rf1n, cp1out, iset1, rfvss or rf2p, rf2n, cp2out, iset2, rfvss on the signal list in section 3. the n and r values for tx and rx modes are synthes iser specific and can be se t from the host c via the c-bus. various synthesiser spec ific status signals are also acce ssible via c-bus. the divide by n counter is 20 bits; the r counter is 13 bits . typical external components are shown in figure 18. both synthesisers are phase locked loops (plls) of the same design, utilising external vcos and loop filters. the vcos need to have good phase noise perform ance although it is likely that the high division ratios used will result in the dominant noise source being the reference oscillator. the phase detectors are of the phase-frequency type with a high impedanc e charge pump output requiring just passive components in the loop filter. lock detec t functions are built in to each synthesiser and the status reported via c-bus. a transition to out-of-lock can be detec ted and communicated via a c-bus interrupt to the host c. this can be important in ensuring that the transmitter cannot transmit in the event of a fault condition arising. two levels of charge pump gain are available to the user , to facilitate the possibility of locking at different rates under program control. a current setting resist or (r31) is connected between the iset pin (one for each pll system) and the respective rfvss pin. th is resistor will have an internally generated band gap voltage expressed across it and may have a value of 0 to 30k , which (in conjunction with the on-chip series resistor of 9.6k ) will give charge pump current settings over a range of 2.5ma down to 230a (including the control bit variation of 4 to 1). the val ue of the current setting resistor (r31) is determined in accordance with the following formulae: gain bit set to 1: r31 (in ?) = (24/i cp ) ? 9600 gain bit cleared to 0: r31 (in ?) = (6/i cp ) ? 9600 where i cp is the charge pump current (in ma). note that the charge pump current should always be set to at least 230a. the ?gain bit? refers to either bit 3 or bit 11 in the rf synthesiser control register, $b3. divide by n counter lock detect divide by r counter charge pump voltage ref detect phase comp - + rfnn rfnp rf s y nthesiser clock mux mux tx n rx n tx r rx r cpnout cpvdd isetn internal clock
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 46 d/7131/41_fi-1.0/7 the step size (comparison frequency) is programmable; to minimise the effects of phase noise this should be kept as high as possible. this can be set as low as 2.5khz (for a reference input of 20mhz or less), or up to 200khz ? limited only by the performance of the phase comparator. the frequency for each synthesiser is se t by using two registers: an ?r? register that sets the division value of the input reference frequency to the compar ison frequency (step size), and an ?n? register that sets the division of the required synthesised fr equency from the external vco to the comparison frequency. this yields the required synthesised frequency (fs), such that: fs = (n / r) x f ref where f ref is the selected reference frequency other parameters for the synthesisers are the charge pump setting (high or low) o since the set-up for the plls takes 4 x ?rf synthesis er data register? writes it follows that, while updating the pll settings, the registers may cont ain unwanted or intermediate values of bits. these will persist until the last register is wr itten. it is intended that users should change the content of the ?rf synthesiser data register? on a pll that is disabled, powersaved or selected to work from the alternate register set (?tx? and ?rx? are alternate register sets). there are no interlocks to enforce this intention. the names ?tx? and ?rx? are arbitrary and may be assigned to other functions as required. they are independent sets of registers, one of which is selected to command each pll by changing the settings in the rf synthesiser control - $b3 write register. for optimum performance, a common master clock should be used for the rf synthesisers (the rf synthesiser clock) and the baseband se ctions (main and auxiliary system clocks). using unsynchronised clocks can result in spurious products being generat ed in the synthesiser output and in some cases difficulty may be experienced with obtai ning lock in the rf synthesisers. lock status the lock status can be observed by reading the rf sy nthesiser status register , $b4, and the individual lock status bits can (subject to masking) provide a c-bus interrupt. the lock detector can use a tolerance of one cycle or f our cycles of the reference clock (not the divided version that is used as a comparison frequency) in or der to judge phase lock. an internal shift register holds the last three lock status m easurements and the lock status bits are flagged according to a majority vote of these previous three states. hence, one occasi onal lock error will not flag a lock fail. at least two successive phase lock events are required for the lock stat us to be true. note that the lock status bits confirm phase lock to the measured tolerance and not frequency lock. the synthesiser may take more time to confirm phase lock with the lock status bits than the time to switch from channel to channel. the purpose of a 4-cycle tolerance is for the case where a high frequency reference oscillator would not forgive a small phase error. rf inputs the rf inputs are differential and self biased (when not powersaved). they are intended to be capacitatively coupled to the rf signal. the si gnal should be in the range 0dbm to ?20dbm (not necessarily balanced). to ensure an accurate i nput signal the rf should be terminated with 50? as close to the chip as possible and with the ?p? and ?n? inputs capacitatively coupled to the input and ground, keeping these connections as short as possible. t he rf input impedance is almost purely capacitative and is dominated by package and prin ted circuit board parasitics. guidelines for using the rf synthesisers ? rf input slew rate (dv/dt) should be 14 v/s minimum. ? the rf synthesiser 2.5v digital supply can be powered from the vdec output pin. ? rf clock sources and other, different clock sources must not share common ic components, as this may introduce coupling into the rf. unused ac-coupled clock buffer circuits should be tied off to a dc supply, to prevent them oscillating. ? it is recommended that the rf synthesisers are oper ated with maximum charge pump gain (ie. iset tied to rfvss). ? the loop filter components should be optimised for each vco.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 47 d/7131/41_fi-1.0/7 7.12 digital system clock generators ref clk div /1 to 512 $ac b0-8 pd vco pll div /1 to 1024 $ab b0-9 lpf sysclk1 ref sysclk1 div vco op div /1 to 64 $ab b10-15 sysclk1 pre-clk $ac b11-15 sysclk1 output 384khz-20mhz 48 - 192khz (96khz typ) sysclk1 vco 24.576- 98.304mhz (49.152mhz typ) ref clk div /1 to 512 $ae b0-8 pd vco pll div /1 to 1024 $ad b0-9 lpf sysclk2 ref sysclk2 div vco op div /1 to 64 $ad b10-15 sysclk2 pre-clk $ae b11-15 sysclk2 output 384khz-20mhz 48 - 192khz (96khz typ) sysclk2 vco 24.576- 98.304mhz (49.152mhz typ) ref clk div /1 to 512 p3.4 pd vco pll div /1 to 1024 p3.5 lpf mainclk ref mainclk div vco op div /1 to 64 p3.3 & 3.6 mainclk pre-clk mainclk output 384khz-50mhz (24.576mhz typ) 48 - 192khz (96khz typ) mainclk vco 24.576- 98.304mhz (49.152mhz typ) to internal adc / dac dividers auxadc div p3.3 & p3.6 aux_adc (83.3khz typ) osc 3.0 - 12.288mhz xtal or 3.0 - 24.576mhz clock to rf synthesiser ref clk selection figure 20 digital clock generation schemes the cmx7131/CMX7141 includes a 2-pin crystal oscillator circuit. this can either be configured as an oscillator, as shown in section 5, or the xtal input can be driven by an externally generated clock. the crystal (xtal) source frequency can go up to 12.288m hz (clock source frequency up to 24.576mhz), but a 19.2mhz oscillator is assumed by defaul t for the functionality provided in the cmx7131/CMX7141. 7.12.1 main clock operation a digital pll is used to create the main clock (nom inally 24.576mhz) for the in ternal sections of the cmx7131/CMX7141. at the same time, other internal clocks are generated by divisi on of either the xtal reference clock or the main clock. these internal clocks are used for determining the sample rates and conversion times of a-to-d and d-to-a converters, running a general purpose (gp) timer and the signal
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 48 d/7131/41_fi-1.0/7 processing block. in particular, it should be noted that in idle mode the setting of the gp timer divider directly affects the c-bus latency (with the default values this is nominally 250 s). the cmx7131/CMX7141 defaults to the settings appropriate for a 19.2mhz oscillator, however if other frequencies are to be used then the program block r egisters p3.2 to p3.7 will need to be programmed appropriately at power-on. this flexibility allows the dev ice to re-use an external clock source, so reducing total cost and potential noise sources. a table of common values is provided in table 4. see: o program block 3 ? auxdac, ramdac and clock control 7.12.2 system clock operation two system clock outputs, sysclk 1 and sysclk2, are available to drive additional circuits, as required. these are digital phase locked loop (pll) cl ocks that can be programmed via the system clock registers with suitable values chosen by the user . the system clock pll configure registers ($ab and $ad) control the values of the vco output divider and main divide registers, while the system clock ref. configure registers ($ac and $ae) control the va lues of the reference divider and signal routing configurations. the plls are designed for a reference frequency of 96khz. if not required, these clocks can be independently powersaved. the clock generation scheme is shown in the block diagram of figure 20. note that at power-on, these pins are disabled. see: o o sysclk 1 and sysclk 2 pll data - $ab, $ad write o sysclk 1 and sysclk 2 ref - $ac and $ae write 7.13 signal level optimisation the internal signal processing of the cmx7131/CMX7141 will operate with wide dynamic range and low distortion only if the signal level at all stages in the signal processing chain is kept within the recommended limits. for a device working from a 3. 3v 10% supply, the maximum signal level which can be accommodated without distortion is [(3.3 x 90%) - (2 x 0.3v)] volts pk-pk = 838mv rms, assuming a sine wave signal. this should not be exceeded at any stage. 7.13.1 transmit path levels for the maximum signal out of the mod1 and mod2 a ttenuators, the signal leve l at the output of the modem block is set to be 0db, the fine output adjus tment ($c8 p4.2-4.3) has a maximum attenuation of 3.5db and no gain, whereas the coarse output adjus tment ($b0) has a variable attenuation of up to +40.0db and no gain. 7.13.2 receive path levels the coarse input adjustment ($b1) has a variable gain of up to +22.4db and no attenuation. with the lowest gain setting (0db), the maximum allowable i nput signal level at the discfb pin would be 838mv rms. this signal level is an absolute maximum, which should not be exceeded.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 49 d/7131/41_fi-1.0/7 7.14 tx spectrum plots the following figure shows the tx spectrum when using a suitable signal generator as measured on a spectrum analyser using the cmx7131/CMX7141 internal prbs generator. note that the i/q mode is sensitive to variations in dc offset in the modulation path and these must be minimised. r e f l v l - 1 8 d b m r e f l v l - 1 8 d b m r b w 5 0 0 h z v b w 2 k h z s w t 7 0 0 m s rf att 10 db a unit dbm 3. 5 k h z / c e n t e r 4 4 6 . 1 m h z span 35 khz 1 v i e w 1 s a - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 1 1 8 - 1 8 1 m a r k e r 1 [ t 1 ] - 7 5 . 8 5 db m 4 4 6 . 0 9 6 3 1 2 5 0 mh z 1 [ t 1 ] -75.85 dbm 446.09631250 mhz c h p w r -21.19 dbm a c p u p -66.25 db a c p l o w -67.42 db a l t 1 u p -83.63 db a l t 1 l ow -84.58 db c l 2 c l 2 c l 1 c l 1 c0 c 0 c u 1 c u 1 cu2 cu2 d a t e : 1 3 : 4 5 : 4 4 ref lvl -18 dbm ref lvl -18 dbm r b w 5 0 0 h z s w t 7 0 0 m s rf att 10 db a unit dbm 3 . 5 k h z / center 446.1 mhz span 35 khz v b w 2 k h z 1 v i e w 1 r m - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 1 1 8 - 1 8 1 marker 1 [t1] -76.3 0 d b m 446.0963125 0 m h z 1 [ t 1] -76.30 dbm 446.09631250 mhz c h p w r -22.02 dbm a c p u p -63.35 db a c p l ow -67.65 db a l t 1 up -74.93 db a l t 1 low -74.22 db cl2 cl2 cl1 cl1 c 0 c 0 c u 1 c u1 cu2 cu2 d a t e : 1 3 : 3 0 : 0 9 two-point modulation spectrum i/q modulation spectrum figure 21 tx modulation spectra - 4800bps r e f l v l - 1 8 d b m r e f l v l - 1 8 d b m r b w 5 0 0 h z v b w 2 k h z s w t 1 . 2 s rf att 10 db a 1 s a unit dbm 6 k h z / c e n t e r 4 4 6 . 1 m h z span 60 khz - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 1 1 8 - 1 8 1 m a r k e r 1 [ t 1 ] - 4 4 . 6 9 db m 4 4 6 . 0 9 6 3 1 2 5 0 mh z 1 [ t 1 ] -44.69 dbm 446.09631250 mhz c h p w r -21.53 dbm a c p u p -74.16 db a c p l o w -71.46 db a l t 1 u p -80.62 db a l t 1 l ow -81.36 db c l 2 c l 2 c l 1 c l 1 c0 c 0 c u 1 cu1 cu2 cu2 d a t e : 1 0 : 2 7 : 5 0 ref lvl -18 dbm ref lvl -18 dbm rf att 10 db a unit dbm center 446.1 mhz span 70 khz 7 k h z / r b w 5 0 0 h z s w t 1 . 4 s v b w 2 k h z 1 r m - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 1 1 8 - 1 8 1 marker 1 [t1] -29.8 7 d b m 446.1001891 3 m h z 1 [ t 1] -29.87 dbm 446.10018913 mhz c h p w r -22.04 dbm a c p u p -67.21 db a c p l ow -68.57 db a l t 1 up -76.83 db a l t 1 low -76.65 db cu2 cu2 c u 1 c u 1 cl1 cl1 cl2 cl2 c 0 c 0 d a t e : 0 9 : 2 2 : 4 4 two-point modulation spectrum i/q modulation spectrum figure 22 tx modulation spectra - 9600bps
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 50 d/7131/41_fi-1.0/7 7.15 c-bus register summary table 9 c-bus registers addr. (hex) register word size (bits) $01 w c-bus reset 0 $a7 w auxadc configuration 16 $a8 w auxdac data and control 16 $a9 r auxadc1 data and status/checksum 2 hi 16 $aa r auxadc2 data and status/checksum 2 lo 16 $ab w sysclk 1 pll data 16 $ac w sysclk 1 ref 16 $ad w sysclk 2 pll data 16 $ae w sysclk 2 ref 16 $af reserved $b0 w analogue output gain 16 $b1 w input gain and signal routing 16 $b2 w rf synthesiser data (cmx7131 only) 16 $b3 w rf synthesiser control (cmx7131 only) 16 $b4 r rf synthesiser status (cmx7131 only) 8 $b5 w txdata 0 16 $b6 w txdata 1 16 $b7 w txdata 2 16 $b8 r rxdata 0/checksum 1 hi 16 $b9 r rxdata 1/checksum 1 lo 16 $ba r rxdata 2 16 $bb r rxdata 3 16 $bc reserved $bd reserved $be reserved $bf reserved $c0 w power down control 16 $c1 w modem control 16 $c2 w auxdata write 16 $c3 w cmx6x8 analogue gain 16 $c4 reserved $c5 r rx data 4 16 $c6 r irq status 16 $c7 w modem configuration 16 $c8 w programming register 16 $c9 r modem status 16 $ca w tx data 3 16 $cb w tx data 4 16 $cc r auxdata read 16 $cd w auxadc threshold data 16 $ce w interrupt mask 16 $cf reserved all other c-bus addresses (including those not list ed above) are either reserved for future use or allocated for production testing and must not be accessed in normal operation.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 51 d/7131/41_fi-1.0/7 8 performance specification 8.1 electrical performance 8.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. unit supply: dv dd - dv ss ? 0.3 4.5 v av dd - av ss ? 0.3 4.5 v rfv dd - rfv ss (cmx7131 only) ? 0.3 4.5 v cpv dd - rfv ss (cmx7131 only) ? 0.3 4.5 v voltage on any pin to dv ss ? 0.3 dv dd + 0.3 v voltage on any pin to av ss ? 0.3 av dd + 0.3 v current into or out of any power supply pin (excluding bias) (i.e.vdec, avdd, avss, dvdd, dvss, cpvdd , rfvddorrfvss ) ? 30 +30 ma current into or out of any other pin ? 20 +20 ma voltage differential between power supplies: dv dd and av dd or cpv dd 0 0.3 v av dd and cpv dd (cmx7131 only) 0 0.3 v dv ss and av ss or rfv ss (cmx7131) 0 50 mv av ss and rfv ss (cmx7131 only) 0 50 mv l4 package (48-pin lqfp) min. max. unit total allowable power dissipation at tamb = 25c ? 1600 mw ... derating ? 16 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c q3 package (48-pin vqfn) min. max. unit total allowable power dissipation at tamb = 25c ? 1750 mw ... derating ? 17.5 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c l9 package (64-pin lqfp) min. max. unit total allowable power dissipation at tamb = 25c ? 1690 mw ? derating ? 16.9 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c q1 package (64-pin vqfn) min. max. unit total allowable power dissipation at tamb = 25c ? 3500 mw ? derating ? 35.0 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 52 d/7131/41_fi-1.0/7 8.1.2 operating limits correct operation of the device outsi de these limits is not implied. notes min. max. unit supply voltage: dv dd ? dv ss 3.0 3.6 v av dd ? av ss 3.0 3.6 v cpv dd ? rfv ss (cmx7131 only) 3.0 3.6 v rfv dd ? dv ss (cmx7131 only) 3 2.25 2.75 v v dec ? dv ss 2 2.25 2.75 v operating temperature ? 40 +85 c xtal/clk frequency (using a xtal) 1 3.0 12.288 mhz xtal/clk frequency (using an external clock) 1 3.0 24.576 mhz notes: 1 nominal xtal/clk frequency is 19.2mhz. 2 the v dec supply is automatically derived from dv dd by the on-chip voltage regulator. 3 the rfv dd supply can be supplied from the v dec supply, if preferred.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 53 d/7131/41_fi-1.0/7 8.1.3 operating characteristics for the following conditions unless otherwise specified: external components as recommended in figure 2. maximum load on digital outputs = 30pf. oscillator frequency = 19.2mhz 0.01% (100ppm); tamb = ? 40c to +85c. av dd = dv dd = cpv dd (cmx7131) = 3.0v to 3.6v; rfv dd (cmx7131) = 2.25v to 2.75v. v dec = 2.5v. reference signal level = 308mvrms at 1khz with av dd = 3.3v. signal levels track with supply voltage, so scale accordingly. signal to noise ratio (snr) in bit rate bandwidth. input stage gain = 0db. output stage attenuation = 0db. current consumption figures quoted in this sect ion apply to the device when loaded with fi-1.x only. the use of other function images, can m odify the current consum ption of the device. dc parameters notes min. typ. max. unit supply current 21 all powersaved di dd ? 8 100 a ai dd ? 4 20 a idle mode 22 di dd ? 1.4 ? ma ai dd 23 ? 1.6 ? ma rx mode 22 di dd (4800bps ? search for fs) ? 4.7 ? ma di dd (9600bps ? search for fs) ? 7.5 ? ma di dd (4800bps ? fs found) ? 2.8 ? ma di dd (9600bps ? fs found) ? 3.7 ? ma ai dd ? 1.6 ? ma tx mode 22 di dd (4800bps ? 2-point) ? 4.3 ? ma di dd (9600bps ? 2-point) ? 5.2 ? ma di dd (4800bps ? i/q) ? 5.4 ? ma di dd (9600bps ? i/q) ? 7.3 ? ma ai dd (av dd = 3.3v) ? 1.5 ? ma additional current for each auxiliary system clock (output running at 4mhz) di dd (dv dd = 3.3v, v dec = 2.5v) ? 250 ? a additional current for each auxiliary adc di dd (dv dd = 3.3v, v dec = 2.5v) ? 50 ? a additional current for each auxiliary dac ai dd (av dd = 3.3v) ? 200 ? a additional current for each rf synthesiser 24 cpi dd + rfi dd (cpv dd = 3.3v, rfv dd = 2.5v) ? 2.5 4.5 ma notes: 21 tamb=25c: not including any current dr awn from the device pins by external circuitry. 22 system clocks: auxiliary circuits disabled, but all other digital circuits (including the main clock pll) enabled. 23 may be further reduced by power-saving unused sections 24 when using the external components shown in figure 18 and when supplying the current for rfv dd from the regulated 2.5v digital (v dec ) supply. the latter is derived from dv dd by an on-chip voltage regulator.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 54 d/7131/41_fi-1.0/7 dc parameters (continued) notes min. typ. max. unit xtal/clk input 25 input logic 1 70% ? ? dv dd input logic 0 ? ? 30% dv dd input current (vin = dv dd ) ? ? 40 a input current (vin = dv ss ) ? 40 ? ? a c-bus interface and logic inputs input logic 1 70% ? ? dv dd input logic 0 ? ? 30% dv dd input leakage current (logic 1 or 0) ? 1.0 ? 1.0 a input capacitance ? ? 7.5 pf c-bus interface and logic outputs output logic 1 (i oh = 2ma) 90% ? ? dv dd output logic 0 (i ol = -5ma) ? ? 10% dv dd ?off? state leakage current ? ? 10 a irqn (vout = dv dd ) ? 1.0 ? +1.0 a reply_data (output hiz) ? 1.0 ? +1.0 a v bias 26 output voltage offset wrt av dd /2 (i ol < 1 a) ? 2% ? av dd output impedance ? 22 ? k notes: 25 characteristics when driving the xtal/clk pin with an external clock source. 26 applies when utilising v bias to provide a reference voltage to other parts of the system. when using v bias as a reference, v bias must be buffered. v bias must always be decoupled with a capacitor as shown in figure 2.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 55 d/7131/41_fi-1.0/7 ac parameters notes min. typ. max. unit xtal/clk input 'high' pulse width 31 15 ? ? ns 'low' pulse width 31 15 ? ? ns input impedance (at 6.144mhz) powered-up resistance ? 150 ? k capacitance ? 20 ? pf powered-down resistance ? 300 ? k capacitance ? 20 ? pf xtal start-up time (from powersave) ? 20 ? ms system clk 1/2 outputs xtal/clk input to clock_out timing: (in high to out high) 32 ? 15 ? ns (in low to out low) 32 ? 15 ? ns 'high' pulse width 33 76 81.38 87 ns 'low' pulse width 33 76 81.38 87 ns v bias start-up time (from powersave) ? 30 ? ms microphone, alternative and discriminator inputs (mic, alt, disc) input impedance 34 ? >10 ? m maximum input level (pk-pk) 35 ? ? 80% av dd load resistance (feedback pins) 80 ? ? k a mplifier open loop voltage gai n ? (i/p = 1mv rms at 100hz) ? ? 80 ? db unity gain bandwidth ? 1.0 ? mhz programmable input gain stage 36 gain (at 0db) 37 ? 0.5 0 +0.5 db cumulative gain error ? (wrt attenuation at 0db) ? 37 ? 1.0 0 +1.0 db notes: 31 timing for an external input to the xtal/clk pin. 32 xtal/clk input driven by an external source. 33 6.144mhz xtal fitted and 6.144mhz out put selected (scale for 19.2mhz). 34 with no external component s connected, measured at dc. 35 centered about av dd /2; after multiplying by the gain of input circuit (with external components connected). 36 gain applied to signal at output of bu ffer amplifier: discfb, altfb or micfb 37 design value. overall attenuation input to output has a tolerance of 0db 1.0db
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 56 d/7131/41_fi-1.0/7 ac parameters notes min. typ. max. unit modulator outputs 1/2 and audio output (mod 1, mod 2, audio) power-up to output stable 41 ? 50 100 s modulator attenuators attenuation (at 0db) 43 ? 1.0 0 +1.0 db cumulative attenuation error ? (wrt attenuation at 0db) ? ? 0.6 0 +0.6 db output impedance ? enabled 42 ? 600 ? ? disabled 42 ? 500 ? k output current range (av dd = 3.3v) ? ? 125 a output voltage range 44 0.5 ? av dd ?0.5 v load resistance 20 ? ? k audio attenuator attenuation (at 0db) 43 ? 1.0 0 +1.0 db cumulative attenuation error ? (wrt attenuation at 0db) ? ? 1.0 0 +1.0 db output impedance ? enabled 42 ? 600 ? ? disabled 42 ? 500 ? k output current range (av dd = 3.3v) ? ? 125 a output voltage range 44 0.5 ? av dd ?0.5 v load resistance 20 ? ? k notes: 41 power-up refers to issuing a c-bus command to turn on an output. these limits apply only if v bias is on and stable. at power s upply switch-on, the default state is for all blocks, except the xtal and c-bus interface, to be in placed in powersave mode. 42 small signal impedance, at av dd = 3.3v and tamb = 25c. 43 with respect to the signal at t he feedback pin of the selected input port. 44 centered about av dd /2; with respect to the output driving a 20k load to av dd /2.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 57 d/7131/41_fi-1.0/7 ac parameters (cont.) notes min. typ. max. unit auxiliary signal inputs (aux adc 1 to 4) source output impedance 51 ? ? 24 k auxiliary 10 bit adcs resolution ? 10 ? bits maximum input level (pk-pk) 54 ? ? 80% av dd conversion time 52 ? 250 ? s input impedance resistance 57 ? >10 ? m capacitance ? 5 ? pf zero error 55 0 ? 10 mv integral non-linearity ? ? 3 lsbs differential non-linearity 53 ? ? 1 lsbs auxiliary 10 bit dacs resolution ? 10 ? bits maximum output level (pk-pk), no load 54 80% ? ? av dd zero error 56 0 ? 10 mv resistive load 5 ? ? k integral non-linearity ? ? 4 lsbs differential non-linearity 53 ? ? 1 lsbs notes: 51 denotes output impedance of the driver of the auxiliary input signal, to ensure < 1 bit additional error under nominal conditions. 52 with an auxiliary clock frequency of 6.144mhz. 53 guaranteed monotonic with no missing codes. 54 centred about av dd /2. 55 input offset from a nominal v bias input, which produces a $0200 adc output. 56 output offset from a $0200 dac input, measured wrt a nominal v bias output. 57 measured at dc.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 58 d/7131/41_fi-1.0/7 ac parameters (cont.) notes min. typ. max. unit rf synthesisers ? phase locked loops 61 reference clock input input logic 1 62 70% ? ? rfv dd input logic 0 62 ? ? 30% rfv dd frequency 64, 66 5.0 19.2 40.0 mhz divide ratios (r) 63 2 ? 8191 each rf synthesiser 69 comparison frequency ? ? 500 khz input frequency range 67 100 ? 600 mhz input level (at 600mhz) ? 15 ? 0 dbm input slew rate 14 ? ? v/s divide ratios (n) 1024 ? 104857 5 1hz normalised phase noise floor 68 ? ? 197 ? dbc/hz charge pump current (i cp ) (high) 65 1.88 2.5 3.3 ma charge pump current (i cp ) (low) 65 470 625 820 a charge pump current ? voltage variation ? 10% ? per v charge pump current ? sink to source match ? 5% ? of i cp notes: 61 parameters only guaranteed for the l9 package. 62 square wave input. 63 separate dividers are provided for each pll. 64 for optimum performance of the synt hesiser subsystems, a common master clock should be used for the rf synthes isers and the baseband sections. using unsynchronised clocks is likely to result in spurious products being generated in the synthesiser outputs and in some ca ses difficulty may be experienced in obtaining lock in the rf synthesisers. 65 external iset resistor (r31) = 0 ? (internal iset resistor = 9k6 ? nominally). 66 lower input frequencies may be used subject to division ratio requirements being maintained. 67 operation outside these frequency limits is possible, but not guaranteed. at lower frequencies slew rate needs to be considered. 68 1hz normalised phase noise floor (p n1hz) can be used to calculate the phase noise within the pll loop by: phase noise (in-band) = pn1hz + 20log 10 (n) + 10log 10 (f comparison ) 69 it is recommended that rf synthesis er 1 be used for the higher frequency use (eg: rf 1 st lo) and rf synthesiser 2 be used for lower frequency use (eg: if lo).
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 59 d/7131/41_fi-1.0/7 8.1.4 parametric performance for the following conditions unless otherwise specified: external components as recommended in figure 2. maximum load on digital outputs = 30pf. oscillator frequency = 19.2mhz 0.01% (100ppm); tamb = ? 40c to +85c. av dd = dv dd = 3.0v to 3.6v. reference signal level = 308mvrms at 1khz with av dd = 3.3v. signal levels track with supply voltage, so scale accordingly. signal to noise ratio (snr) in bit rate bandwidth. input stage gain = 0db, out put stage attenuation = 0db. all figures quoted in this section apply to the dev ice when loaded with fi-1.x only. the use of other function images, can modify the parametric performance of the device. ac parameters (cont.) notes min. typ. max. unit modem symbol rate 2400 ? 4800 symbols /sec modulation 4fsk filter (rc) alpha ? 0.2 ? tx output level (mod1, mod2 , 2-point) 70 ? 2.88 ? vpk-pk tx output level (mod1, mod2, i/q) 70 ? 2.20 ? vpk-pk tx adjacent channel power (mod1, mod2, prbs) 71, 73 -60 ? ? db rx sensitivity (ber 4800 sy mbols/sec) 72 ? tbd ? dbm rx co-channel rejection 71, 73 15 12 ? db rx input level ? ? 838 mvrms rx input dc offset 0.5 ? av dd - 0.5 v notes: 70 transmitting continuous default preamble. 71 see user manual section 7.14. 72 measured at baseband ? radio design will affect ultimate product performance. 73 for a 6.25khz/4800bps channel.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 60 d/7131/41_fi-1.0/7 8.2 c-bus timing figure 23 c-bus timing c-bus timing notes min. typ. max. unit t cse csn enable to sclk high time 100 ? ? ns t csh last sclk high to csn high time 100 ? ? ns t loz sclk low to rdata output enable time 0.0 ? ? ns t hiz csn high to rdata high impedance ? ? 1.0 s t csoff csn high time between transactions 1.0 ? ? s t nxt inter-byte time 200 ? ? ns t ck sclk cycle time 200 ? ? ns t ch sclk high time 100 ? ? ns t cl sclk low time 100 ? ? ns t cds cdata setup time 75 ? ? ns t cdh cdata hold time 25 ? ? ns t rds rdata setup time 50 ? ? ns t rdh rdata hold time 0 ? ? ns notes: 1. depending on the command, 1 or 2 bytes of cdata are transmitted to the peripheral msb (bit 7) first, lsb (bit 0) las t. rdata is read from the peripher al msb (bit 7) first, lsb (bit 0) last. 2. data is clocked into the peripheral on the rising sclk edge. 3. commands are acted upon at the end of each command (rising edge of csn). 4. to allow for differing c serial interface formats c-bus compatible ics are able to work with sclk pulses starting and ending at either polarity. 5. maximum 30pf load on irqn pin and each c-bus interface line. these timings are for the latest version of c-bus and allow faster transfers than the original c-bus timing specification. the cmx7131/CMX7141 can be used in conjunction with devices that comply with the slower timings, subject to system throughput constraints.
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 61 d/7131/41_fi-1.0/7 8.3 packaging figure 24 mechanical outline of 64-pin vqfn (q1) order as part no. cmx7131q1 figure 25 mechanical outline of 64-pin lqfp (l9) order as part no. cmx7131l9
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 62 d/7131/41_fi-1.0/7 figure 26 mechanical outline of 48-pin lqfp (l4) order as part no. CMX7141l4 figure 27 mechanical outline of 48-pin vqfn (q3) order as part no. CMX7141q3 as package dimensions may change after publication of this datasheet, it is recommended that you check for the latest packaging information from the design support/package information page of the cml website: [www.cmlmicro.com].
digital pmr radio processor cmx7131/CMX7141 ? 2009 cml microsystems plc page 63 d/7131/41_fi-1.0/7 about firmasic ? cml?s proprietary firmasic ? component technology reduces cost, ti me to market and development risk, with increased flexibility for the designer and end application. firmasic ? combines analogue, digital, firmware and memory technologies in a single silicon pl atform that can be focused to deliver the right feature mix, performance and price for a target application family. specific functions of a firmasic ? device are determined by uploading its function image? during device initialization. new function images? may be later provided to s upplement and enhance device functions, expanding or modifying end-product features without the need for expensive and time-consuming design changes. firmasic ? devices provide significant time to market and commercial benefits over custom asic, structured asic, fpga and dsp solutions. they may al so be exclusively customised where security or intellectual property issues prevent the use of application specific standard products (assp?s). handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. cml does not assume any responsibility for the use of any circuitry descri bed. no ipr or circu it patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of testing every product shi pped using calibrated test equipment to ensure compliance with thi s product specification. specific testing of a ll circuit parameters is not necessarily performed.

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